idt72t40108.vhd

VHDL的ram和fifo model code 包含众多的厂家

                        SO_zd := tmp_ser_in(fs_Incnt);
                        fs_Incnt:=fs_Incnt+1;
                    END IF;
                    IF fs_Incnt >= 30 THEN
                        fs_Incnt:=0;
                    END IF;
                ELSIF memory_model = normal THEN
                    IF fs_Incnt < 32 THEN
                        SO_zd := tmp_ser_in(fs_Incnt);
                        fs_Incnt:=fs_Incnt+1;
                    END IF;
                    IF fs_Incnt >= 32 THEN
                        fs_Incnt:=0;
                    END IF;
                END IF;
            END IF;

            END read_register;

        BEGIN

    ----------------------------------------------------------------------------
    -- Timing Check Section
    ----------------------------------------------------------------------------
    IF (TimingChecksOn) THEN

        -- tDS, tDH
        VitalSetupHoldCheck (
            TestSignal      => DIn,
            TestSignalName  => "D",
            RefSignal       => WCLKIn,
            RefSignalName   => "WCLK",
            SetupHigh       => tsetup_D0_WCLK,
            SetupLow        => tsetup_D0_WCLK,
            HoldHigh        => thold_D0_WCLK,
            HoldLow         => thold_D0_WCLK,
            CheckEnabled    => (WENNegIn='0' AND WCSNegIn='0'),
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_D_WCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_D_WCLK
        );

        VitalSetupHoldCheck (
            TestSignal      => DIn,
            TestSignalName  => "D",
            RefSignal       => WCLKIn,
            RefSignalName   => "WCLK",
            SetupHigh       => tsetup_D0_WCLK,
            SetupLow        => tsetup_D0_WCLK,
            HoldHigh        => thold_D0_WCLK,
            HoldLow         => thold_D0_WCLK,
            CheckEnabled    => (WENNegIn='0' AND WCSNegIn='0' AND mode_wr=DDR),
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_D_WCLK_DDR,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_D_WCLK_DDR
        );

        -- tENS, tENH
        VitalSetupHoldCheck (
            TestSignal      => RENNegIn,
            TestSignalName  => "RENNeg",
            RefSignal       => RCLKIn,
            RefSignalName   => "RCLK",
            SetupHigh       => tsetup_RENNeg_RCLK,
            SetupLow        => tsetup_RENNeg_RCLK,
            HoldHigh        => thold_RENNeg_RCLK,
            HoldLow         => thold_RENNeg_RCLK,
            CheckEnabled    => (RCSNegIn='0' AND RENNegIn='0'),
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_RENNeg_RCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_RENNeg_RCLK
        );

        VitalSetupHoldCheck (
            TestSignal      => WENNegIn,
            TestSignalName  => "WENNeg",
            RefSignal       => WCLKIn,
            RefSignalName   => "WCLK",
            SetupHigh       => tsetup_RENNeg_RCLK,
            SetupLow        => tsetup_RENNeg_RCLK,
            HoldHigh        => thold_RENNeg_RCLK,
            HoldLow         => thold_RENNeg_RCLK,
            CheckEnabled    => (WCSNegIn='0' AND WENNegIn='0'),
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_WENNeg_WCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_WENNeg_WCLK
        );

        VitalSetupHoldCheck (
            TestSignal      => RCSNegIn,
            TestSignalName  => "RCSNeg",
            RefSignal       => RCLKIn,
            RefSignalName   => "RCLK",
            SetupHigh       => tsetup_RENNeg_RCLK,
            SetupLow        => tsetup_RENNeg_RCLK,
            HoldHigh        => thold_RENNeg_RCLK,
            HoldLow         => thold_RENNeg_RCLK,
            CheckEnabled    => (RCSNegIn='0' AND RENNegIn='0'),
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_RCSNeg_RCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_RCSNeg_RCLK
        );

        VitalSetupHoldCheck (
            TestSignal      => RTNegIn,
            TestSignalName  => "RTNeg",
            RefSignal       => RCLKIn,
            RefSignalName   => "RCLK",
            SetupHigh       => tsetup_RENNeg_RCLK,
            SetupLow        => tsetup_RENNeg_RCLK,
            HoldHigh        => thold_RENNeg_RCLK,
            HoldLow         => thold_RENNeg_RCLK,
            CheckEnabled    => true,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_RTNeg_RCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_RTNeg_RCLK
        );

        VitalSetupHoldCheck (
            TestSignal      => MARKIn,
            TestSignalName  => "MARK",
            RefSignal       => RCLKIn,
            RefSignalName   => "RCLK",
            SetupHigh       => tsetup_RENNeg_RCLK,
            SetupLow        => tsetup_RENNeg_RCLK,
            HoldHigh        => thold_RENNeg_RCLK,
            HoldLow         => thold_RENNeg_RCLK,
            CheckEnabled    => true,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_MARK_RCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_MARK_RCLK
        );

        -- tWCSS, tWCSH
        VitalSetupHoldCheck (
            TestSignal      => WCSNegIn,
            TestSignalName  => "WCSNeg",
            RefSignal       => WCLKIn,
            RefSignalName   => "WCLK",
            SetupHigh       => tsetup_WCSNeg_WCLK,
            SetupLow        => tsetup_WCSNeg_WCLK,
            HoldHigh        => thold_WCSNeg_WCLK,
            HoldLow         => thold_WCSNeg_WCLK,
            CheckEnabled    => (WCSNegIn='0'),
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_WCSNeg_WCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_WCSNeg_WCLK
        );

        -- tSDS, tSDH
        VitalSetupHoldCheck (
            TestSignal      => SIIn,
            TestSignalName  => "SI",
            RefSignal       => SCLKIn,
            RefSignalName   => "SCLK",
            SetupHigh       => tsetup_SI_SCLK,
            SetupLow        => tsetup_SI_SCLK,
            HoldHigh        => thold_SI_SCLK,
            HoldLow         => thold_SI_SCLK,
            CheckEnabled    => true,
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_SI_SCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_SI_SCLK
        );

        -- tSENS, tSENH
        VitalSetupHoldCheck (
            TestSignal      => SENNegIn,
            TestSignalName  => "SENNeg",
            RefSignal       => SCLKIn,
            RefSignalName   => "SCLK",
            SetupHigh       => tsetup_SENNeg_SCLK,
            SetupLow        => tsetup_SENNeg_SCLK,
            HoldHigh        => thold_SENNeg_SCLK,
            HoldLow         => thold_SENNeg_SCLK,
            CheckEnabled    => (SENNeg = '0'),
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_SENNeg_SCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_SENNeg_SCLK
        );

        VitalSetupHoldCheck (
            TestSignal      => SRENNegIn,
            TestSignalName  => "SRENNeg",
            RefSignal       => SCLKIn,
            RefSignalName   => "SCLK",
            SetupHigh       => tsetup_SENNeg_SCLK,
            SetupLow        => tsetup_SENNeg_SCLK,
            HoldHigh        => thold_SENNeg_SCLK,
            HoldLow         => thold_SENNeg_SCLK,
            CheckEnabled    => (SRENNeg = '0'),
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_SRENNeg_SCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_SRENNeg_SCLK
        );

        -- tRSS
        VitalSetupHoldCheck (
            TestSignal      => RENNegIn,
            TestSignalName  => "RENNeg",
            RefSignal       => MRSNegIn,
            RefSignalName   => "MRSNeg",
            SetupHigh       => tsetup_RENNeg_MRSNeg,
            CheckEnabled    => true,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_RENNeg_MRSNeg,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_RENNeg_MRSNeg
        );

        VitalSetupHoldCheck (
            TestSignal      => WENNegIn,
            TestSignalName  => "WENNeg",
            RefSignal       => MRSNegIn,
            RefSignalName   => "MRSNeg",
            SetupHigh       => tsetup_RENNeg_MRSNeg,
            CheckEnabled    => true,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_WENNeg_MRSNeg,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_WENNeg_MRSNeg
        );

        VitalSetupHoldCheck (
            TestSignal      => SENNegIn,
            TestSignalName  => "SENNeg",
            RefSignal       => MRSNegIn,
            RefSignalName   => "MRSNeg",
            SetupHigh       => tsetup_RENNeg_MRSNeg,
            CheckEnabled    => true,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_SENNeg_MRSNeg,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_SENNeg_MRSNeg
        );

        VitalSetupHoldCheck (
            TestSignal      => SRENNegIn,
            TestSignalName  => "SRENNeg",
            RefSignal       => MRSNegIn,
            RefSignalName   => "MRSNeg",
            SetupHigh       => tsetup_RENNeg_MRSNeg,
            CheckEnabled    => true,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_SRENNeg_MRSNeg,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_SRENNeg_MRSNeg
        );

        VitalSetupHoldCheck (
            TestSignal      => FWFTIn,
            TestSignalName  => "FWFT",
            RefSignal       => MRSNegIn,
            RefSignalName   => "MRSNeg",
            SetupHigh       => tsetup_RENNeg_MRSNeg,
            SetupLow        => tsetup_RENNeg_MRSNeg,
            CheckEnabled    => true,
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_FWFT_MRSNeg,
            XOn             => XOn,
            MsgOn