idt72t40108.vhd

VHDL的ram和fifo model code 包含众多的厂家

            EFNegOut => EFNeg,
            ERCLKOut => ERCLK,
            ERENNegOut => ERENNeg,
            FFNegOut => FFNeg,
            PAENegOut => PAENeg,
            PAFNegOut => PAFNeg,
            SOOut => SO
        );

    SIGNAL Q_zd : std_logic_vector(39 downto 0) := (others => 'Z');
    SIGNAL mreset :  boolean := false;
    SIGNAL time_flag_for_OE : std_logic := '0';

    TYPE mode_type IS (SDR, DDR);
    TYPE match_type IS (DDR40, DDR20, DDR10, SDR40, SDR20, SDR10);
    TYPE offset_type IS ARRAY (0 TO 3) OF positive;
    TYPE last_done_type is (write, read, none);
    TYPE memory_model_type is (normal, mapped);

    BEGIN
        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Fifo : PROCESS (DIn, BMIn, WCLKIn, MRSNegIn, PRSNegIn, FWFTIn,
                        OWIn, FSEL0In, FSEL1In, WENNegIn, IWIn, RTNegIn,
                        OENegIn, RENNegIn, SENNegIn, RCLKIn, HSTLIn, MARKIn,
                        RCSNegIn, RSDRNegIn, SCLKIn, SRENNegIn, SIIn, WCSNegIn,
                        WSDRNegIn)

            CONSTANT offsetps : offset_type := (7, 127, 63, 255);

            -- Timing Check Variables
            VARIABLE Tviol_D_WCLK        : X01 := '0';
            VARIABLE TD_D_WCLK           : VitalTimingDataType;

            VARIABLE Tviol_D_WCLK_DDR    : X01 := '0';
            VARIABLE TD_D_WCLK_DDR       : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_RCLK   : X01 := '0';
            VARIABLE TD_RENNeg_RCLK      : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_WCLK   : X01 := '0';
            VARIABLE TD_WENNeg_WCLK      : VitalTimingDataType;

            VARIABLE Tviol_RCSNeg_RCLK   : X01 := '0';
            VARIABLE TD_RCSNeg_RCLK      : VitalTimingDataType;

            VARIABLE Tviol_RTNeg_RCLK    : X01 := '0';
            VARIABLE TD_RTNeg_RCLK       : VitalTimingDataType;

            VARIABLE Tviol_MARK_RCLK     : X01 := '0';
            VARIABLE TD_MARK_RCLK        : VitalTimingDataType;

            VARIABLE Tviol_WCSNeg_WCLK   : X01 := '0';
            VARIABLE TD_WCSNeg_WCLK      : VitalTimingDataType;

            VARIABLE Tviol_SI_SCLK       : X01 := '0';
            VARIABLE TD_SI_SCLK          : VitalTimingDataType;

            VARIABLE Tviol_SENNeg_SCLK   : X01 := '0';
            VARIABLE TD_SENNeg_SCLK      : VitalTimingDataType;

            VARIABLE Tviol_SRENNeg_SCLK  : X01 := '0';
            VARIABLE TD_SRENNeg_SCLK     : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_RENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_WENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_SENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_SENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_SRENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_SRENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_FWFT_MRSNeg   : X01 := '0';
            VARIABLE TD_FWFT_MRSNeg      : VitalTimingDataType;

            VARIABLE Tviol_FSEL1_MRSNeg  : X01 := '0';
            VARIABLE TD_FSEL1_MRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_FSEL0_MRSNeg  : X01 := '0';
            VARIABLE TD_FSEL0_MRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_BM_MRSNeg     : X01 := '0';
            VARIABLE TD_BM_MRSNeg        : VitalTimingDataType;

            VARIABLE Tviol_OW_MRSNeg     : X01 := '0';
            VARIABLE TD_OW_MRSNeg        : VitalTimingDataType;

            VARIABLE Tviol_IW_MRSNeg     : X01 := '0';
            VARIABLE TD_IW_MRSNeg        : VitalTimingDataType;

            VARIABLE Tviol_WSDRNeg_MRSNeg : X01 := '0';
            VARIABLE TD_WSDRNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_RSDRNeg_MRSNeg : X01 := '0';
            VARIABLE TD_RSDRNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_RTNeg_MRSNeg  : X01 := '0';
            VARIABLE TD_RTNeg_MRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_HSTL_MRSNeg   : X01 := '0';
            VARIABLE TD_HSTL_MRSNeg      : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_PRSNeg : X01 := '0';
            VARIABLE TD_RENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_PRSNeg : X01 := '0';
            VARIABLE TD_WENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_SENNeg_PRSNeg : X01 := '0';
            VARIABLE TD_SENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_SRENNeg_PRSNeg : X01 := '0';
            VARIABLE TD_SRENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_RTNeg_PRSNeg  : X01 := '0';
            VARIABLE TD_RTNeg_PRSNeg     : VitalTimingDataType;

            VARIABLE Rviol_RENNeg_MRSNeg : X01 := '0';
            VARIABLE RD_RENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Rviol_WENNeg_MRSNeg : X01 := '0';
            VARIABLE RD_WENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Rviol_FWFT_MRSNeg   : X01 := '0';
            VARIABLE RD_FWFT_MRSNeg      : VitalTimingDataType;

            VARIABLE Rviol_WSDRNeg_MRSNeg : X01 := '0';
            VARIABLE RD_WSDRNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Rviol_RSDRNeg_MRSNeg : X01 := '0';
            VARIABLE RD_RSDRNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Rviol_RENNeg_PRSNeg : X01 := '0';
            VARIABLE RD_RENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Rviol_WENNeg_PRSNeg : X01 := '0';
            VARIABLE RD_WENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Pviol_MRSNeg        : X01 := '0';
            VARIABLE PD_MRSNeg    : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_PRSNeg        : X01 := '0';
            VARIABLE PD_PRSNeg    : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_RCLK1          : X01 := '0';
            VARIABLE PD_RCLK1      : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_RCLK2          : X01 := '0';
            VARIABLE PD_RCLK2      : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_WCLK1          : X01 := '0';
            VARIABLE PD_WCLK1      : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_WCLK2          : X01 := '0';
            VARIABLE PD_WCLK2      : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_SCLK          : X01 := '0';
            VARIABLE PD_SCLK      : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE mode_wr     : mode_type := SDR;
            VARIABLE mode_rd     : mode_type := SDR;

            VARIABLE in_mode     : match_type := SDR40;
            VARIABLE out_mode    : match_type := SDR40;

            VARIABLE wrote_in   : boolean := false;
            VARIABLE read_out   : boolean := false;

            -- Memory array declaration
            TYPE MemStore IS ARRAY (0 to TotalLOC + 1) OF INTEGER
                             RANGE -2 TO MaxData;
                                            -- uninitialized memory -2
                                            -- unknown or corrupted memory -1
            -- Functionality Results Variables
            VARIABLE Violation    : X01 := '0';

            VARIABLE EFNeg_zd    : std_ulogic;
            VARIABLE FFNeg_zd    : std_ulogic;
            VARIABLE PAFNeg_dly  : std_ulogic;
            VARIABLE PAFNeg_zd   : std_ulogic;
            VARIABLE PAENeg_dly  : std_ulogic;
            VARIABLE PAENeg_zd   : std_ulogic;
            VARIABLE ERCLK_zd    : std_ulogic;
            VARIABLE ERENNeg_zd  : std_ulogic;
            VARIABLE Qreg   : std_logic_vector(39 downto 0) := (others => '0');
            VARIABLE Qreg_tmp: std_logic_vector(39 downto 0):=(others => '0');
            VARIABLE rtreg   : std_logic_vector(39 downto 0) := (others => '0');
            VARIABLE SO_zd   : std_ulogic;

            VARIABLE fwft         : boolean := false;
            VARIABLE bm           : boolean := false;
            VARIABLE iw           : boolean := false;
            VARIABLE ow           : boolean := false;
            VARIABLE memA         : MemStore;
            VARIABLE memB         : MemStore;
            VARIABLE memC         : MemStore;
            VARIABLE memD         : MemStore;
            VARIABLE Data1        : Integer := 0;
            VARIABLE Data2        : Integer := 0;
            VARIABLE Data3        : Integer := 0;
            VARIABLE Data4        : Integer := 0;

            VARIABLE memory_model : memory_model_type := normal;
            VARIABLE rdptr    : natural RANGE 0 TO TotalLOC + 1
                                                            := 0; --read pointer
            VARIABLE wrptr    : natural RANGE 0 TO TotalLOC + 1
                                                            := 0;--write pointer
            VARIABLE rdptr_next : natural RANGE 0 TO TotalLOC + 1
                                                            := 0; --read pointer
            VARIABLE wrptr_next : natural RANGE 0 TO TotalLOC + 1
                                                            := 0;--write pointer
            VARIABLE rtrdptr  : natural RANGE 0 TO TotalLOC + 1;--retransmit pt.
            VARIABLE paeoff   : natural RANGE 0 TO TotalLOC; --pae offset
            VARIABLE pafoff   : natural RANGE 0 TO TotalLOC; --paf offset
            VARIABLE opi      : natural RANGE 0 TO 7; --offset preset index
            VARIABLE count    : natural RANGE 0 TO TotalLOC + 1; --memory used
            VARIABLE fwftcnt  : natural RANGE 0 TO 3;  -- fwft RCLK counter
            VARIABLE fwftcnt1 : natural RANGE 0 TO 3;  -- fwft output
            VARIABLE fwftvar  : boolean := false;  -- fwft flag for outreg
            VARIABLE opireg   : std_logic_vector(1 downto 0);
            VARIABLE outreg   : std_logic_vector(39 downto 0);
            VARIABLE outtmp   : std_logic_vector(39 downto 0);
            VARIABLE rd_upd_flg : boolean := false;
            VARIABLE wr_upd_flg : boolean := false;

            VARIABLE rt_mode    : boolean := false;
            VARIABLE rtrdptr_set : boolean := false;
            VARIABLE rdptr_set : boolean := false;

            VARIABLE write_clk_paf : Natural := 0;
            VARIABLE read_clk_pae  : Natural := 0;
            VARIABLE delayed_pae : boolean := false;
            VARIABLE delayed_paf : boolean := false;

            VARIABLE Eflagcnt   : natural   := 0;
            VARIABLE PAEflagcnt : natural   := 0;
            VARIABLE PAFflagcnt : natural   := 0;
            VARIABLE Fflagcnt   : natural   := 0;

            VARIABLE TotalLoc1: natural := TotalLoc;

            VARIABLE tRCLKposedge : Time := 0 ns;
            VARIABLE tWCLKposedge : Time := 0 ns;
            VARIABLE tRCLKnegedge : Time := 0 ns;
            VARIABLE tWCLKnegedge : Time := 0 ns;
            VARIABLE tOEnegedge : Time := 0 ns;
            VARIABLE minskew1RW   : boolean := true;
            VARIABLE minskew2RW   : boolean := true;
            VARIABLE minskew3RW   : boolean := true;
            VARIABLE minskew1WR   : boolean := true;
            VARIABLE minskew2WR   : boolean := true;
            VARIABLE minskew3WR   : boolean := true;
            VARIABLE last_done            : last_done_type := none;
            VARIABLE flag_FF              : std_logic := '0';
            VARIABLE flag_EF              : std_logic := '0';
            VARIABLE flag_PAF             : std_logic := '0';
            VARIABLE flag_PAE             : std_logic := '0';
            VARIABLE pass_EF, pass_FF, pass_PAE, pass_PAF   : boolean := false;

            VARIABLE bm_reg   : std_logic_vector(2 downto 0);
            VARIABLE bm_Incnt : natural RANGE 0 TO 7 := 0;
            VARIABLE bm_Outcnt: natural RANGE 0 TO 7 := 0;

            VARIABLE fs_Incnt : natural RANGE 0 to 32 := 0;
            VARIABLE tmp_ser_in     : std_logic_vector(31 downto 0) :=
                                                        (OTHERS=>'0');

            -- Output Glitch Detection Variables
            VARIABLE FFNeg_GlitchData  : VitalGlitchDataType;
            VARIABLE PAFNeg_GlitchData : VitalGlitchDataType;
            VARIABLE EFNeg_GlitchData  : VitalGlitchDataType;
            VARIABLE PAENeg_GlitchData : VitalGlitchDataType;
            VARIABLE ERCLK_GlitchData  : VitalGlitchDataType;
            VARIABLE ERENNeg_GlitchData : VitalGlitchDataType;
            VARIABLE SO_GlitchData : VitalGlitchDataType;

            PROCEDURE master_reset
            IS
            BEGIN
                mreset <= false, true AFTER 30 ns; -- valid reset signal
                fwftcnt := 0;
                PAENeg_zd := '0';
                PAFNeg_zd := '1';
                PAENeg_dly := '0';
                PAFNeg_dly := '1';
                TotalLoc1 := TotalLoc;
                rdptr := 0;
                wrptr := 0;
                count := 0;
                last_done := none;
                rt_mode := false;
                -- configuration section
                IF FWFTIn = '1' THEN
                    fwft := true;       -- fwft mode
                    EFNeg_zd := '1';
                    FFNeg_zd := '0';
                ELSE
                    fwft := false;       --idt standard mode
                    EFNeg_zd := '0';
                    FFNeg_zd := '1';
                END IF;
                IF BMIn = '0' THEN