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📄 idt72821.ftm

📁 VHDL的ram和fifo model code 包含众多的厂家
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<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for IDT72821 Parts</TITLE><REVISION.HISTORY>version: |  author:  | mod date: | changes made:  V1.0     R. Munden   99 MAY 11   Initial release</REVISION.HISTORY></HEAD><BODY><TIMESCALE>1ns</TIMESCALE><MODEL>IDT72821<FMFTIME>IDT72821L10PF<SOURCE>IDT data sheet December 1998</SOURCE>IDT72821L10TF<SOURCE>IDT data sheet December 1998</SOURCE><COMMENT>The Values listed are for VCC=4.5V to 5.5V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH RSNeg  EFNeg  (2:7:10) (2:7:10))     (IOPATH RCLK   EFNeg  (2:4:6.5) (2:4:6.5))     (IOPATH RCLK   PAENeg (2:4:6.5) (2:4:6.5))     (IOPATH WCLK   FFNeg  (2:4:6.5) (2:4:6.5))     (IOPATH WCLK   PAFNeg (2:4:6.5) (2:4:6.5))     (IOPATH RSNeg  Q0     (2:7:10) (2:7:10) (2:7:10) (2:7:10) (2:7:10) (2:7:10))     (IOPATH RCLK   Q0     (2:5:6.5) (2:5:6.5) (2:5:6.5) (2:5:6.5) (2:5:6.5) (2:5:6.5))     (IOPATH OENeg  Q0     (2:4:6) (2:4:6) (3:4:6) (2:4:6) (3:4:6) (2:4:6))  ))  (TIMINGCHECK   (PERIOD (posedge RCLK) (10))   (PERIOD (posedge WCLK) (10))   (WIDTH  (posedge RCLK) (4.5))   (WIDTH  (negedge RCLK) (4.5))   (WIDTH  (negedge RSNeg) (10))   (SETUPHOLD D0  (posedge WCLK) (3) (0.5))   (SETUPHOLD REN1Neg (posedge RCLK) (3) (0.5))   (SETUP REN1Neg (posedge RSNeg) (8))  )) (CELL (CELLTYPE "VITALbuf")     (INSTANCE %LABEL%/SKEW1) (DELAY  (ABSOLUTE ( DEVICE  (5) ) ) ) ) (CELL (CELLTYPE "VITALbuf" )     (INSTANCE %LABEL%/SKEW2) (DELAY  (ABSOLUTE ( DEVICE  (14) ) ) )</TIMING></FMFTIME><FMFTIME>IDT72821L12PF<SOURCE>IDT data sheet December 1998</SOURCE>IDT72821L12TF<SOURCE>IDT data sheet December 1998</SOURCE><COMMENT>The Values listed are for VCC=4.5V to 5.5V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH RSNeg  EFNeg  (3:9:12) (3:9:12))     (IOPATH RCLK   EFNeg  (2:6:8) (2:6:8))     (IOPATH RCLK   PAENeg (2:6:8) (2:6:8))     (IOPATH WCLK   FFNeg  (2:6:8) (2:6:8))     (IOPATH WCLK   PAFNeg (2:6:8) (2:6:8))     (IOPATH RSNeg  Q0     (3:9:12) (3:9:12) (3:9:12) (3:9:12) (3:9:12) (3:9:12))     (IOPATH RCLK   Q0     (2:6:8) (2:6:8) (2:6:8) (2:6:8) (2:6:8) (2:6:8))     (IOPATH OENeg  Q0     (3:6:7) (3:6:7) (3:6:7) (3:6:7) (3:6:7) (3:6:7))  ))  (TIMINGCHECK   (PERIOD (posedge RCLK) (12))   (PERIOD (posedge WCLK) (12))   (WIDTH  (posedge RCLK) (5))   (WIDTH  (negedge RCLK) (5))   (WIDTH  (negedge RSNeg) (12))   (SETUPHOLD D0  (posedge WCLK) (3) (0.5))   (SETUPHOLD REN1Neg (posedge RCLK) (3) (0.5))   (SETUP REN1Neg (posedge RSNeg) (9))  )) (CELL (CELLTYPE "VITALbuf")     (INSTANCE %LABEL%/SKEW1) (DELAY  (ABSOLUTE ( DEVICE  (5) ) ) ) ) (CELL (CELLTYPE "VITALbuf" )     (INSTANCE %LABEL%/SKEW2) (DELAY  (ABSOLUTE ( DEVICE  (14) ) ) )</TIMING></FMFTIME><FMFTIME>IDT72821L15PF<SOURCE>IDT data sheet December 1998</SOURCE>IDT72821L15TF<SOURCE>IDT data sheet December 1998</SOURCE><COMMENT>The Values listed are for VCC=4.5V to 5.5V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH RSNeg  EFNeg  (3:10:15) (3:10:15))     (IOPATH RCLK   EFNeg  (2:6:10) (2:6:10))     (IOPATH RCLK   PAENeg (2:6:10) (2:6:10))     (IOPATH WCLK   FFNeg  (2:6:10) (2:6:10))     (IOPATH WCLK   PAFNeg (2:6:10) (2:6:10))     (IOPATH RSNeg  Q0     (3:10:15) (3:10:15) (3:10:15) (3:10:15) (3:10:15) (3:10:15))     (IOPATH RCLK   Q0     (2:6:10) (2:6:10) (2:6:10) (2:6:10) (2:6:10) (2:6:10))     (IOPATH OENeg  Q0     (3:6:8) (3:6:8) (3:6:8) (3:6:8) (3:6:8) (3:6:8))  ))  (TIMINGCHECK   (PERIOD (posedge RCLK) (15))   (PERIOD (posedge WCLK) (15))   (WIDTH  (posedge RCLK) (6))   (WIDTH  (negedge RCLK) (6))   (WIDTH  (negedge RSNeg) (15))   (SETUPHOLD D0  (posedge WCLK) (4) (1))   (SETUPHOLD REN1Neg (posedge RCLK) (4) (1))   (SETUP REN1Neg (posedge RSNeg) (10))  )) (CELL (CELLTYPE "VITALbuf")     (INSTANCE %LABEL%/SKEW1) (DELAY  (ABSOLUTE ( DEVICE  (6) ) ) ) ) (CELL (CELLTYPE "VITALbuf" )     (INSTANCE %LABEL%/SKEW2) (DELAY  (ABSOLUTE ( DEVICE  (15) ) ) )</TIMING></FMFTIME><FMFTIME>IDT72821L25PF<SOURCE>IDT data sheet December 1998</SOURCE>IDT72821L25TF<SOURCE>IDT data sheet December 1998</SOURCE><COMMENT>The Values listed are for VCC=4.5V to 5.5V, CL=30pF, Ta=0 to 70 Celsius</COMMENT><COMMENT>Typical values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE     (IOPATH RSNeg  EFNeg  (4:18:25) (4:18:25))     (IOPATH RCLK   EFNeg  (2:10:15) (2:10:15))     (IOPATH RCLK   PAENeg (2:10:15) (2:10:15))     (IOPATH WCLK   FFNeg  (2:10:15) (2:10:15))     (IOPATH WCLK   PAFNeg (2:10:15) (2:10:15))     (IOPATH RSNeg  Q0     (4:18:25) (4:18:25) (4:18:25) (4:18:25) (4:18:25) (4:18:25))     (IOPATH RCLK   Q0     (2:10:15) (2:10:15) (2:10:15) (2:10:15) (2:10:15) (2:10:15))     (IOPATH OENeg  Q0     (3:8:13) (3:8:13) (3:8:13) (3:8:13) (3:8:13) (3:8:13))  ))  (TIMINGCHECK   (PERIOD (posedge RCLK) (25))   (PERIOD (posedge WCLK) (25))   (WIDTH  (posedge RCLK) (10))   (WIDTH  (negedge RCLK) (10))   (WIDTH  (negedge RSNeg) (15))   (SETUPHOLD D0  (posedge WCLK) (6) (1))   (SETUPHOLD REN1Neg (posedge RCLK) (6) (1))   (SETUP REN1Neg (posedge RSNeg) (15))  )) (CELL (CELLTYPE "VITALbuf")     (INSTANCE %LABEL%/SKEW1) (DELAY  (ABSOLUTE ( DEVICE  (10) ) ) ) ) (CELL (CELLTYPE "VITALbuf" )     (INSTANCE %LABEL%/SKEW2) (DELAY  (ABSOLUTE ( DEVICE  (18) ) ) )</TIMING></FMFTIME></BODY></FTML>

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