idt723642.vhd

VHDL的ram和fifo model code 包含众多的厂家

    -- Pulse Width Check Variables
      VARIABLE Pviol_CLKA          : X01 := '0';
      VARIABLE PD_CLKA             : VitalPeriodDataType := VitalPeriodDataInit;

      VARIABLE Pviol_CLKB          : X01 := '0';
      VARIABLE PD_CLKB             : VitalPeriodDataType := VitalPeriodDataInit;
  
      -- Setup/Hold Check Variables
      VARIABLE Tviol_A0_CLKA       : X01 := '0';     --------A
      VARIABLE TD_A0_CLKA          : VitalTimingDataType;

      VARIABLE TViol_B0_CLKB       : X01 := '0';    ------------B
      VARIABLE TD_B0_CLKB          : VitalTimingDataType;
  ---------------------------------------------------------tab0-1,tens
    VARIABLE Tviol_CSANeg_CLKA   : X01 := '0';        --------A
      VARIABLE TD_CSANeg_CLKA      : VitalTimingDataType;

      VARIABLE Tviol_WRA_CLKA      : X01 := '0';      --------A
      VARIABLE TD_WRA_CLKA         : VitalTimingDataType;
      
       VARIABLE Tviol_CSBNeg_CLKB   : X01 := '0';  ------------B
      VARIABLE TD_CSBNeg_CLKB      : VitalTimingDataType;

      VARIABLE Tviol_WRB_CLKB      : X01 := '0';   ------------B
      VARIABLE TD_WRB_CLKB         : VitalTimingDataType;
    -------------------------------------------------------------------  
      VARIABLE Tviol_ENA_CLKA      : X01 := '0';--------A
      VARIABLE TD_ENA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_ENB_CLKB     : X01 := '0'; ------------B
      VARIABLE TD_ENB_CLKB        : VitalTimingDataType;
      
      VARIABLE Tviol_MBA_CLKA      : X01 := '0';--------A
      VARIABLE TD_MBA_CLKA         : VitalTimingDataType;

      
      VARIABLE Tviol_MBB_CLKB     : X01 := '0'; ------------B
      VARIABLE TD_MBB_CLKB        : VitalTimingDataType;
      ----------------------------------------------------------trsth,tab o-1
      VARIABLE Tviol_RST1Neg_CLKA   : X01 := '0';
      VARIABLE TD_RST1Neg_CLKA      : VitalTimingDataType;
      
      VARIABLE Tviol_RST2Neg_CLKA   : X01 := '0';
      VARIABLE TD_RST2Neg_CLKA      : VitalTimingDataType;
      
      VARIABLE Tviol_RST1Neg_CLKB   : X01 := '0';
      VARIABLE TD_RST1Neg_CLKB      : VitalTimingDataType;
   
      VARIABLE Tviol_RST2Neg_CLKB   : X01 := '0';
      VARIABLE TD_RST2Neg_CLKB      : VitalTimingDataType;
   
    -----------------------------------------------------------------------  
      VARIABLE Tviol_FS0_RST1Neg    : X01 := '0';
      VARIABLE TD_FS0_RST1Neg       : VitalTimingDataType;

      VARIABLE Tviol_FS1_RST1Neg    : X01 := '0';
      VARIABLE TD_FS1_RST1Neg       : VitalTimingDataType;
      
      VARIABLE Tviol_FS0_RST2Neg    : X01 := '0';
      VARIABLE TD_FS0_RST2Neg       : VitalTimingDataType;

      VARIABLE Tviol_FS1_RST2Neg    : X01 := '0';
      VARIABLE TD_FS1_RST2Neg       : VitalTimingDataType;

    -- Violation variable (used to OR all individual violation variables)

      VARIABLE Violation           : X01 := '0';

BEGIN

--------------------------------------------------------------------------------
-- Timing Check Section                                                       --
--------------------------------------------------------------------------------
 IF  (TimingChecksOn)
 THEN

      -- CLKA period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKA,
          TestSignalName  => "CLKA",
          Period	  => tperiod_CLKA_posedge,
          PulseWidthHigh  => tpw_CLKA_posedge,
          PulseWidthLow   => tpw_CLKA_negedge,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,
          PeriodData      => PD_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Pviol_CLKA);

      -- CLKB period and pulse width check(high & low)

      VitalPeriodPulseCheck (
          TestSignal      => CLKB,
          TestSignalName  => "CLKB",
          Period	  => tperiod_CLKB_posedge,
          PulseWidthHigh  => tpw_CLKB_posedge,
          PulseWidthLow   => tpw_CLKB_negedge,
          CheckEnabled    => TRUE,
          HeaderMsg       => InstancePath & partID,
          PeriodData      => PD_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Pviol_CLKB);
  
   -- A/CLKA setup/hold time checks

      VitalSetupHoldCheck (
          TestSignal      => A_ipd,
          TestSignalName  => "A",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tsetup_A0_CLKA,
          SetupLow        => tsetup_A0_CLKA,
          HoldHigh        => thold_A0_CLKA,
          HoldLow         => thold_A0_CLKA,
          CheckEnabled    => (CSANeg = '0') AND (WRA = '1') AND (ENA = '1'),
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_A0_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_A0_CLKA);

   -- B/CLKB setup/hold time checks

      VitalSetupHoldCheck (
          TestSignal      => B_ipd,
          TestSignalName  => "B",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tsetup_B0_CLKB,
          SetupLow        => tsetup_B0_CLKB,
          HoldHigh        => thold_B0_CLKB,
          HoldLow         => thold_B0_CLKB,
          CheckEnabled    => (CSBNeg = '0') AND (WRB = '0') AND (ENB = '1'),
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_B0_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => TViol_B0_CLKB);

      -- CSANeg/CLKA setup/hold time check   

      VitalSetupHoldCheck (
          TestSignal      => CSANeg,
          TestSignalName  => "CSANeg",
          RefSignal       => CLKA,  
          RefSignalName   => "CLKA",
          SetupHigh       => tsetup_CSANeg_CLKA,
          SetupLow        => tsetup_CSANeg_CLKA,
          HoldHigh        => thold_CSANeg_CLKA,
          HoldLow         => thold_CSANeg_CLKA,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_CSANeg_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_CSANeg_CLKA);
  
      -- WRA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => WRA,
          TestSignalName  => "WRA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tsetup_WRA_CLKA,
          SetupLow        => tsetup_WRA_CLKA,
          HoldHigh        => thold_WRA_CLKA,
          HoldLow         => thold_WRA_CLKA,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_WRA_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_WRA_CLKA);
          
      -- CSBNeg/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => CSBNeg,
          TestSignalName  => "CSBNeg",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tsetup_CSBNeg_CLKB,
          SetupLow        => tsetup_CSBNeg_CLKB,
          HoldHigh        => thold_CSBNeg_CLKB,
          HoldLow         => thold_CSBNeg_CLKB,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_CSBNeg_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_CSBNeg_CLKB);
  
      -- WRB/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => WRB,
          TestSignalName  => "WRB",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tsetup_WRB_CLKB,
          SetupLow        => tsetup_WRB_CLKB,
          HoldHigh        => thold_WRB_CLKB,
          HoldLow         => thold_WRB_CLKB,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_WRB_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_WRB_CLKB);

      -- ENA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => ENA,
          TestSignalName  => "ENA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tsetup_ENA_CLKA,
          SetupLow        => tsetup_ENA_CLKA,
          HoldHigh        => thold_ENA_CLKA,
          HoldLow         => thold_ENA_CLKA,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_ENA_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_ENA_CLKA);
          
          -- ENB/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => ENB,
          TestSignalName  => "ENB",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tsetup_ENB_CLKB,
          SetupLow        => tsetup_ENB_CLKB,
          HoldHigh        => thold_ENB_CLKB,
          HoldLow         => thold_ENB_CLKB,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_ENB_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_ENB_CLKB);
          
          -- MBA/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MBA,
          TestSignalName  => "MBA",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tsetup_MBA_CLKA,
          SetupLow        => tsetup_MBA_CLKA,
          HoldHigh        => thold_MBA_CLKA,
          HoldLow         => thold_MBA_CLKA,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MBA_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_MBA_CLKA);
          
          -- MBB/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MBB,
          TestSignalName  => "MBB",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tsetup_MBB_CLKB,
          SetupLow        => tsetup_MBB_CLKB,
          HoldHigh        => thold_MBB_CLKB,
          HoldLow         => thold_MBB_CLKB,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MBB_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_MBB_CLKB);

      -- RST2Neg/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => RST2Neg,
          TestSignalName  => "RST2Neg",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tsetup_RST2Neg_CLKA,
          SetupLow        => tsetup_RST2Neg_CLKA,
          HoldHigh        => thold_RST2Neg_CLKA,
          HoldLow         => thold_RST2Neg_CLKA,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_RST2Neg_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_RST2Neg_CLKA);
          -- RST1Neg/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => RST1Neg,
          TestSignalName  => "RST1Neg",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tsetup_RST1Neg_CLKA,
          SetupLow        => tsetup_RST1Neg_CLKA,
          HoldHigh        => thold_RST1Neg_CLKA,
          HoldLow         => thold_RST1Neg_CLKA,
          CheckEnabled    => True,
          RefTransition   => '/',