idt723611.vhd

VHDL的ram和fifo model code 包含众多的厂家

-- CSANeg/CLKA setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => CSANeg,
                TestSignalName  => "CSANeg",
                RefSignal       => CLKA,
                RefSignalName   => "CLKA",
                SetupLow        => tsetup_CSANeg_CLKA,
                HoldLow         => thold_CSANeg_CLKA,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_CSANeg_CLKA,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_CSANeg_CLKA);
-- CSBNeg/CLKB setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => CSBNeg,
                TestSignalName  => "CSBNeg",
                RefSignal       => CLKB,
                RefSignalName   => "CLKB",
                SetupLow        => tsetup_CSANeg_CLKA,
                HoldLow         => thold_CSANeg_CLKA,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_CSBNeg_CLKB,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_CSBNeg_CLKB);
-- W/RANeg/CLKA setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => WRANeg,
                TestSignalName  => "WRANeg",
                RefSignal       => CLKA,
                RefSignalName   => "CLKA",
                SetupHigh       => tsetup_CSANeg_CLKA,
                HoldHigh        => thold_CSANeg_CLKA,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_WRANeg_CLKA,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_WRANeg_CLKA);
-- W/RBNeg/CLKB setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => WRBNeg,
                TestSignalName  => "WRBNeg",
                RefSignal       => CLKB,
                RefSignalName   => "CLKB",
                SetupHigh       => tsetup_CSANeg_CLKA,
                HoldHigh        => thold_CSANeg_CLKA,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_WRBNeg_CLKB,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_WRBNeg_CLKB);

-- ENA_CLKA setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => ENA,
                TestSignalName  => "ENA",
                RefSignal       => CLKA,
                RefSignalName   => "CLKA",
                SetupHigh       => tsetup_ENA_CLKA,
                SetupLow        => tsetup_ENA_CLKA,
                HoldHigh        => thold_ENA_CLKA,
                HoldLow         => thold_ENA_CLKA,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_ENA_CLKA,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_ENA_CLKA);
-- ENB_CLKB setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => ENB,
                TestSignalName  => "ENB",
                RefSignal       => CLKB,
                RefSignalName   => "CLKB",
                SetupHigh       => tsetup_ENA_CLKA,
                SetupLow        => tsetup_ENA_CLKA,
                HoldHigh        => thold_ENA_CLKA,
                HoldLow         => thold_ENA_CLKA,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_ENB_CLKB,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_ENB_CLKB);
-- MBA/CLKA setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => MBA,
                TestSignalName  => "MBA",
                RefSignal       => CLKA,
                RefSignalName   => "CLKA",
                SetupLow        => tsetup_MBA_CLKA,
                HoldLow         => thold_MBA_CLKA,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_MBA_CLKA,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_MBA_CLKA);
-- MBB/CLKB setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => MBB,
                TestSignalName  => "MBB",
                RefSignal       => CLKB,
                RefSignalName   => "CLKB",
                SetupLow        => tsetup_MBA_CLKA,
                HoldLow         => thold_MBA_CLKA,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_MBB_CLKB,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_MBB_CLKB);

-- ODD/EVENNeg/CLKB setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => OddEVENNeg,
                TestSignalName  => "OddEVENNeg",
                RefSignal       => CLKB,
                RefSignalName   => "CLKB",
                SetupHigh       => tsetup_OddEVENNeg_CLKB,
                SetupLow        => tsetup_OddEVENNeg_CLKB,
                HoldHigh        => thold_OddEVENNeg_CLKB,
                HoldLow         => thold_OddEVENNeg_CLKB,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_OddEVENNeg_CLKB,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_OddEVENNeg_CLKB);
-- PGB/CLKB setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => PGB,
                TestSignalName  => "PGB",
                RefSignal       => CLKB,
                RefSignalName   => "CLKB",
                SetupHigh       => tsetup_OddEVENNeg_CLKB,
                SetupLow        => tsetup_OddEVENNeg_CLKB,
                HoldHigh        => thold_OddEVENNeg_CLKB,
                HoldLow         => thold_OddEVENNeg_CLKB,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_PGB_CLKB,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_PGB_CLKB);
-- RSTNeg/CLKA setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => RSTNeg,
                TestSignalName  => "RSTNeg",
                RefSignal       => CLKA,
                RefSignalName   => "CLKA",
                SetupLow        => tsetup_RSTNeg_CLKA,
                HoldLow         => thold_RSTNeg_CLKA,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_RSTNeg_CLKA,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_RSTNeg_CLKA);

-- RSTNeg/CLKB setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => RSTNeg,
                TestSignalName  => "RSTNeg",
                RefSignal       => CLKB,
                RefSignalName   => "CLKB",
                SetupLow        => tsetup_RSTNeg_CLKA,
                HoldLow         => thold_RSTNeg_CLKA,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_RSTNeg_CLKB,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_RSTNeg_CLKB);
-- FS0/RSTNeg setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => FS0,
                TestSignalName  => "FS0",
                RefSignal       => RSTNeg,
                RefSignalName   => "RSTNeg",
                SetupHigh       => tsetup_FS0_RSTNeg,
                SetupLow        => tsetup_FS0_RSTNeg,
                HoldHigh        => thold_FS0_RSTNeg,
                HoldLow         => thold_FS0_RSTNeg,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_FS0_RSTNeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_FS0_RSTNeg);
-- FS1/RSTNeg setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => FS1,
                TestSignalName  => "FS1",
                RefSignal       => RSTNeg,
                RefSignalName   => "RSTNeg",
                SetupHigh       => tsetup_FS0_RSTNeg,
                SetupLow        => tsetup_FS0_RSTNeg,
                HoldHigh        => thold_FS0_RSTNeg,
                HoldLow         => thold_FS0_RSTNeg,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_FS1_RSTNeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_FS1_RSTNeg);

----------------------------------------------------------------------------
-- Functionality Section
----------------------------------------------------------------------------

    Violation :=
             Tviol_A0_CLKA               OR
             Tviol_B0_CLKB               OR
             Tviol_CSANeg_CLKA           OR
             Tviol_CSBNeg_CLKB           OR
             Tviol_WRANeg_CLKA           OR
             Tviol_WRBNeg_CLKB           OR
             Tviol_ENA_CLKA              OR
             Tviol_ENB_CLKB              OR
             Tviol_MBA_CLKA              OR
             Tviol_MBB_CLKB              OR
             Tviol_OddEVENNeg_CLKB       OR
             Tviol_PGB_CLKB              OR
             Tviol_RSTNeg_CLKA           OR
             Tviol_FS0_RSTNeg            OR
             Tviol_A0_CLKA               OR
             Tviol_CSANeg_CLKA           OR
             Tviol_ENA_CLKA              OR
             Tviol_MBA_CLKA              OR
             Tviol_OddEVENNeg_CLKB       OR
             Tviol_RSTNeg_CLKA           OR
             Tviol_RSTNeg_CLKB           OR
             Tviol_FS0_RSTNeg            OR
             Tviol_FS1_RSTNeg            OR
             Pviol_CLKA                  OR
             Pviol_CLKB;

       ASSERT Violation = '0'
                REPORT InstancePath & partID & ": simulation may be" &
                                " inaccurate due to timing violations"
                SEVERITY WARNING;

    -- reset
    IF falling_edge(RSTNeg) THEN
       RST_FLEG:='1';
       reseted :='0';
       MBF1Neg_z