idt723611.vhd

VHDL的ram和fifo model code 包含众多的厂家

        TYPE MemStore IS ARRAY (0 to TotalLOC) OF INTEGER
                         RANGE  -2 TO MaxData;
        SIGNAL READMAIL1   : std_ulogic :='0';
        SIGNAL READMAIL2   : std_ulogic :='0';

        SHARED VARIABLE RDPoint    : NATURAL RANGE 0 TO TotalLoc := 0;
        SHARED VARIABLE WRPoint    : NATURAL RANGE 0 TO TotalLoc := 0;
        SHARED VARIABLE Count      : NATURAL RANGE 0 TO TotalLoc +1 := 1;
        SHARED VARIABLE MemDataL    : MemStore;
        SHARED VARIABLE MemDataH    : MemStore;
        SHARED VARIABLE  Outtput_Reg_A :std_logic_vector(35 DOWNTO 0)
                        :=(OTHERS => '0');
        SHARED VARIABLE  Outtput_Reg_B :std_logic_vector(35 DOWNTO 0)
                        :=(OTHERS => '0');
        SHARED VARIABLE  POM_Z :std_logic_vector(35 DOWNTO 0)
                        :=(OTHERS => 'Z');

        BEGIN
--------------------------------------------------------------------
-- Timing Check Section
--------------------------------------------------------------------
        VITALTimingCheck: PROCESS (AIn,BIn,CLKA,CLKB,CSANeg,CSBNeg,
                                   ENA,ENB,FS1,FS0,MBA,MBB,ODDEVENNeg,
                                   PGA,PGB,RSTNeg,WRANeg,WRBNeg )

--Setup/Hold checks variables

           VARIABLE Tviol_A0_CLKA          : X01 := '0';
           VARIABLE Tviol_B0_CLKB          : X01 := '0';
           VARIABLE Tviol_CSANeg_CLKA      : X01 := '0';
           VARIABLE Tviol_CSBNeg_CLKB      : X01 := '0';
           VARIABLE Tviol_WRANeg_CLKA     : X01 := '0';
           VARIABLE Tviol_WRBNeg_CLKB     : X01 := '0';
           VARIABLE Tviol_ENA_CLKA         : X01 := '0';
           VARIABLE Tviol_ENB_CLKB         : X01 := '0';
           VARIABLE Tviol_MBA_CLKA         : X01 := '0';
           VARIABLE Tviol_MBB_CLKB         : X01 := '0';
           VARIABLE Tviol_OddEVENNeg_CLKB : X01 := '0';
           VARIABLE Tviol_PGB_CLKB         : X01 := '0';
           VARIABLE Tviol_RSTNeg_CLKA      : X01 := '0';
           VARIABLE Tviol_RSTNeg_CLKB      : X01 := '0';
           VARIABLE Tviol_FS0_RSTNeg       : X01 := '0';
           VARIABLE Tviol_FS1_RSTNeg       : X01 := '0';

           VARIABLE TD_A0_CLKA             : VitalTimingDataType;
           VARIABLE TD_B0_CLKB             : VitalTimingDataType;
           VARIABLE TD_CSANeg_CLKA         : VitalTimingDataType;
           VARIABLE TD_CSBNeg_CLKB         : VitalTimingDataType;
           VARIABLE TD_WRANeg_CLKA        : VitalTimingDataType;
           VARIABLE TD_WRBNeg_CLKB        : VitalTimingDataType;
           VARIABLE TD_ENA_CLKA            : VitalTimingDataType;
           VARIABLE TD_ENB_CLKB            : VitalTimingDataType;
           VARIABLE TD_MBA_CLKA            : VitalTimingDataType;
           VARIABLE TD_MBB_CLKB            : VitalTimingDataType;
           VARIABLE TD_OddEVENNeg_CLKB    : VitalTimingDataType;
           VARIABLE TD_PGB_CLKB            : VitalTimingDataType;
           VARIABLE TD_RSTNeg_CLKA         : VitalTimingDataType;
           VARIABLE TD_RSTNeg_CLKB         : VitalTimingDataType;
           VARIABLE TD_FS0_RSTNeg          : VitalTimingDataType;
           VARIABLE TD_FS1_RSTNeg          : VitalTimingDataType;
-- Pulse Width and Period Check Variables

           VARIABLE Pviol_CLKA : X01 := '0';
           VARIABLE PD_CLKA
                    : VitalPeriodDataType := VitalPeriodDataInit;
           VARIABLE Pviol_CLKB : X01 := '0';
           VARIABLE PD_CLKB
                    : VitalPeriodDataType := VitalPeriodDataInit;

           -- Functionality Results Variables
           VARIABLE Violation       : X01 := '0';
           VARIABLE IN_FFNeg        : std_ulogic;
           VARIABLE IN_EFNeg        : std_ulogic;
           VARIABLE IN_AFNeg        : std_ulogic;
           VARIABLE IN_AENeg        : std_ulogic;
           VARIABLE RST_FLEG        : std_ulogic;
           VARIABLE FF_FLEG         : std_ulogic;
           VARIABLE IN_MBF1Neg      : std_ulogic;
           VARIABLE IN_MBF2Neg      : std_ulogic;
           VARIABLE Parity_Data     : std_logic_vector(35 downto 0);
           VARIABLE reseted         : std_ulogic;
           VARIABLE COUNTB          : INTEGER :=0;
           VARIABLE COUNTA          : INTEGER :=0;
           VARIABLE FL_MBF1         : INTEGER :=0;
           VARIABLE FL_MBF2         : INTEGER :=0;
       PROCEDURE PARITY_CHECKING (
                                      Port_Side  : IN INTEGER;
                                      FLEG       : IN INTEGER;
                                      DataIn     : IN
                                      std_logic_vector(35 downto 0)) IS
           VARIABLE INTER      : INTEGER :=0;
           VARIABLE ParityLow  : std_logic :='0';
           VARIABLE Check      : std_logic_vector( 8 downto 0):=(OTHERS=>'0');
           BEGIN
            IF FLEG = 0 THEN
               INTER := 0;
                    FOR i IN 1 TO 4 LOOP
                        IF INTER =0 THEN
                            IF (i= 1 ) THEN
                                Check (8 downto 0)  := DataIn(8 downto 0);
                            END IF;
                            IF  (i= 2 ) THEN
                                Check (8 downto 0)  := DataIn(17 downto 9);
                            END IF;
                            IF (i= 3 ) THEN
                                Check (8 downto 0)  := DataIn(26 downto 18);
                            END IF;
                            IF  (i= 4 ) THEN
                                Check (8 downto 0)  := DataIn(35 downto 27);
                            END IF;
                            ParityLow := '0';
                            FOR j IN 0 TO 8 LOOP
                                IF Check (j) = '1'  THEN
                                    IF ParityLow  = '0' THEN
                                       ParityLow := '1';
                                    ELSE
                                       ParityLow := '0';
                                    END IF;
                                END IF;
                           END LOOP;
                           IF (ParityLow = '0' AND OddEVENNeg = '0') OR
                              (ParityLow = '1' AND OddEVENNeg = '1') THEN

                               IF Port_Side = 0 THEN
                                  PEFANeg_zd <= '1';
                               ELSE
                                  PEFBNeg_zd <= '1';
                               END IF;
                           ELSE
                               IF Port_Side = 0 THEN
                                  PEFANeg_zd <= '0';
                                  INTER :=1;
                               ELSE
                                  PEFBNeg_zd <= '0';
                                  INTER :=1;
                               END IF;
                           END IF;
                        END IF;
                END LOOP;
           ELSE
               IF Port_Side = 0 THEN
                  PEFANeg_zd <= '1';
               ELSE
                  PEFBNeg_zd <= '1';
               END IF;
           END IF;
           END PARITY_CHECKING;

           PROCEDURE PARITY_GENERATION( Port_Side   : IN INTEGER ;
                                        ODD_OR_EVEN : IN std_logic;
                                        DataIn      : IN
                                        std_logic_vector(35 downto 0) ) IS
               VARIABLE Poz        : INTEGER :=0;
               VARIABLE ParityLow  : std_logic :='0';
               VARIABLE Check      : std_logic_vector( 8 downto 0)
                                     :=(OTHERS=>'0');
               VARIABLE DataOut    : std_logic_vector( 35 downto 0)
                                     :=(OTHERS=>'0');
           BEGIN
              DataOut ( 35 downto 0) := DataIn ( 35 downto 0);
              FOR i IN 0 TO 3 LOOP
                            IF (i= 0 ) THEN
                                Check (8 downto 0)  := DataIn(8 downto 0);
                            END IF;
                            IF  (i= 1 ) THEN
                                Check (8 downto 0)  := DataIn(17 downto 9);
                            END IF;
                            IF (i= 2 ) THEN
                                Check (8 downto 0)  := DataIn(26 downto 18);
                            END IF;
                            IF  (i= 3 ) THEN
                                Check (8 downto 0)  := DataIn(35 downto 27);
                            END IF;
                            ParityLow := '0';
                            FOR j IN 0 TO 7 LOOP
                                IF Check (j) = '1'  THEN
                                    IF ParityLow  = '0' THEN
                                       ParityLow := '1';
                                    ELSE
                                       ParityLow := '0';
                                    END IF;
                                END IF;
                           END LOOP;
                           IF (ParityLow = '0' AND OddEVENNeg = '1') OR
                              (ParityLow = '1' AND OddEVENNeg = '0') THEN
                               Poz:= 8 + i*9;
                               DataOut (Poz) := '1';
                           ELSE
                               Poz:= 8 + i*9;
                               DataOut (Poz) := '0';
                           END IF;

                END LOOP;
                IF Port_Side = 0 THEN
                   Outtput_Reg_A( 35 downto 0) := DataOut ( 35 downto 0);
                   AOut_zd <= DataOut ( 35 downto 0);
                ELSE
                   Outtput_Reg_B( 35 downto 0) := DataOut ( 35 downto 0);
                   BOut_zd <= DataOut ( 35 downto 0);
                END IF;
           END PARITY_GENERATION;
       BEGIN
 --------------------------------
 -- Timing Check Section
  --------------------------------

 -- CLKA pulse ( low&high ) width and period check
            VitalPeriodPulseCheck (
                TestSignal      => CLKA,
                TestSignalName  => "CLKA",
                Period          => tperiod_CLKA,
                PulseWidthHigh  => tpw_CLKA_posedge,
                PulseWidthLow   => tpw_CLKA_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_CLKA,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_CLKA);
-- CLKB pulse ( low&high ) width and period check
            VitalPeriodPulseCheck (
                TestSignal      => CLKB,
                TestSignalName  => "CLKB",
                Period          => tperiod_CLKB,
                PulseWidthHigh  => tpw_CLKB_posedge,
                PulseWidthLow   => tpw_CLKB_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_CLKB,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_CLKB);

-- A0/CLKA setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => AIn,
                TestSignalName  => "A",
                RefSignal       => CLKA,
                RefSignalName   => "CLKA",
                SetupHigh       => tsetup_A0_CLKA,
                SetupLow        => tsetup_A0_CLKA,
                HoldHigh        => thold_A0_CLKA,
                HoldLow         => thold_A0_CLKA,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_A0_CLKA,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_A0_CLKA);

-- B0/CLKB setup/hold time check
             VitalSetupHoldCheck (
                TestSignal      => BIn,
                TestSignalName  => "B",
                RefSignal       => CLKB,
                RefSignalName   => "CLKB",
                SetupHigh       => tsetup_A0_CLKA,
                SetupLow        => tsetup_A0_CLKA,
                HoldHigh        => thold_A0_CLKA,
                HoldLow         => thold_A0_CLKA,
                CheckEnabled    => TRUE,
                RefTransition    => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_B0_CLKB,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_B0_CLKB);