idt723611.vhd

VHDL的ram和fifo model code 包含众多的厂家

        w_52 : VitalWireDelay  ( A35_ipd        ,A35      ,tipd_A35);
        w_53 : VitalWireDelay  ( B0_ipd         ,B0       ,tipd_B0 );
        w_54 : VitalWireDelay  ( B1_ipd         ,B1       ,tipd_B1 );
        w_55 : VitalWireDelay  ( B2_ipd         ,B2       ,tipd_B2 );
        w_56 : VitalWireDelay  ( B3_ipd         ,B3       ,tipd_B3 );
        w_57 : VitalWireDelay  ( B4_ipd         ,B4       ,tipd_B4 );
        w_58 : VitalWireDelay  ( B5_ipd         ,B5       ,tipd_B5 );
        w_59 : VitalWireDelay  ( B6_ipd         ,B6       ,tipd_B6 );
        w_60 : VitalWireDelay  ( B7_ipd         ,B7       ,tipd_B7 );
        w_61 : VitalWireDelay  ( B8_ipd         ,B8       ,tipd_B8 );
        w_62 : VitalWireDelay  ( B9_ipd         ,B9       ,tipd_B9 );
        w_63 : VitalWireDelay  ( B10_ipd        ,B10      ,tipd_B10);
        w_64 : VitalWireDelay  ( B11_ipd        ,B11      ,tipd_B11);
        w_65 : VitalWireDelay  ( B12_ipd        ,B12      ,tipd_B12);
        w_66 : VitalWireDelay  ( B13_ipd        ,B13      ,tipd_B13);
        w_67 : VitalWireDelay  ( B14_ipd        ,B14      ,tipd_B14);
        w_68 : VitalWireDelay  ( B15_ipd        ,B15      ,tipd_B15);
        w_69 : VitalWireDelay  ( B16_ipd        ,B16      ,tipd_B16);
        w_70 : VitalWireDelay  ( B17_ipd        ,B17      ,tipd_B17);
        w_71 : VitalWireDelay  ( B18_ipd        ,B18      ,tipd_B18);
        w_72 : VitalWireDelay  ( B19_ipd        ,B19      ,tipd_B19);
        w_73 : VitalWireDelay  ( B20_ipd        ,B20      ,tipd_B20);
        w_74 : VitalWireDelay  ( B21_ipd        ,B21      ,tipd_B21);
        w_75 : VitalWireDelay  ( B22_ipd        ,B22      ,tipd_B22);
        w_76 : VitalWireDelay  ( B23_ipd        ,B23      ,tipd_B23);
        w_77 : VitalWireDelay  ( B24_ipd        ,B24      ,tipd_B24);
        w_78 : VitalWireDelay  ( B25_ipd        ,B25      ,tipd_B25);
        w_79 : VitalWireDelay  ( B26_ipd        ,B26      ,tipd_B26);
        w_80 : VitalWireDelay  ( B27_ipd        ,B27      ,tipd_B27);
        w_81 : VitalWireDelay  ( B28_ipd        ,B28      ,tipd_B28);
        w_82 : VitalWireDelay  ( B29_ipd        ,B29      ,tipd_B29);
        w_83 : VitalWireDelay  ( B30_ipd        ,B30      ,tipd_B30);
        w_84 : VitalWireDelay  ( B31_ipd        ,B31      ,tipd_B31);
        w_85 : VitalWireDelay  ( B32_ipd        ,B32      ,tipd_B32);
        w_86 : VitalWireDelay  ( B33_ipd        ,B33      ,tipd_B33);
        w_87 : VitalWireDelay  ( B34_ipd        ,B34      ,tipd_B34);
        w_88 : VitalWireDelay  ( B35_ipd        ,B35      ,tipd_B35);

     END BLOCK WireDelay;
Behavior: BLOCK
        PORT (
        CLKA             :  IN    std_logic    := 'U';
        CLKB             :  IN    std_logic    := 'U';
        CSANeg           :  IN    std_logic    := 'U';
        CSBNeg           :  IN    std_logic    := 'U';
        ENA              :  IN    std_logic    := 'U';
        ENB              :  IN    std_logic    := 'U';
        FS0              :  IN    std_logic    := 'U';
        FS1              :  IN    std_logic    := 'U';
        MBA              :  IN    std_logic    := 'U';
        MBB              :  IN    std_logic    := 'U';
        OddEVENNeg       :  IN    std_ulogic   := 'U';
        PGA              :  IN    std_ulogic   := 'U';
        PGB              :  IN    std_ulogic   := 'U';
        RSTNeg           :  IN    std_ulogic   := 'U';
        WRANeg           :  IN    std_ulogic   := 'U';
        WRBNeg           :  IN    std_ulogic   := 'U';
        AIn              :  IN    std_logic_vector(35 downto 0):=(OTHERS=>'Z');
        BIn              :  IN    std_logic_vector(35 downto 0):=(OTHERS=>'Z');
        AOut             :  OUT   std_logic_vector(35 downto 0):=(OTHERS=>'Z');
        BOut             :  OUT   std_logic_vector(35 downto 0):=(OTHERS=>'Z');
        AENeg            :  OUT    std_ulogic := 'U';
        AFNeg            :  OUT    std_ulogic := 'U';
        EFNeg            :  OUT   std_ulogic := 'U';
        FFNeg            :  OUT   std_ulogic := 'U';
        MBF1Neg          :  OUT   std_ulogic := 'U';
        MBF2Neg          :  OUT   std_ulogic := 'U';
        PEFANeg          :  OUT   std_ulogic := 'U';
        PEFBNeg          :  OUT   std_ulogic := 'U'
  );
    PORT MAP (
            CLKA    =>  CLKA_ipd,
            CLKB    =>  CLKB_ipd,
            CSANeg  => CSANeg_ipd,
            CSBNeg  => CSBNeg_ipd,
            ENA     => ENA_ipd,
            ENB     => ENB_ipd,
            FS0     => FS0_ipd,
            FS1     => FS1_ipd,
            MBA     => MBA_ipd,
            MBB     => MBB_ipd,
            OddEVENNeg  =>    OddEVENNeg_ipd,
            PGA     => PGA_ipd,
            PGB     => PGB_ipd,
            RSTNeg  => RSTNeg_ipd,
            WRANeg => WRANeg_ipd,
            WRBNeg => WRBNeg_ipd,
            AIn(0)  => A0_ipd,
            AIn(1)  => A1_ipd,
            AIn(2)  => A2_ipd,
            AIn(3)  => A3_ipd,
            AIn(4)  => A4_ipd,
            AIn(5)  => A5_ipd,
            AIn(6)  => A6_ipd,
            AIn(7)  => A7_ipd,
            AIn(8)  => A8_ipd,
            AIn(9)  => A9_ipd,
            AIn(10) => A10_ipd,
            AIn(11) => A11_ipd,
            AIn(12) => A12_ipd,
            AIn(13) => A13_ipd,
            AIn(14) => A14_ipd,
            AIn(15) => A15_ipd,
            AIn(16) => A16_ipd,
            AIn(17) => A17_ipd,
            AIn(18) => A18_ipd,
            AIn(19) => A19_ipd,
            AIn(20) => A20_ipd,
            AIn(21) => A21_ipd,
            AIn(22) => A22_ipd,
            AIn(23) => A23_ipd,
            AIn(24) => A24_ipd,
            AIn(25) => A25_ipd,
            AIn(26) => A26_ipd,
            AIn(27) => A27_ipd,
            AIn(28) => A28_ipd,
            AIn(29) => A29_ipd,
            AIn(30) => A30_ipd,
            AIn(31) => A31_ipd,
            AIn(32) => A32_ipd,
            AIn(33) => A33_ipd,
            AIn(34) => A34_ipd,
            AIn(35) => A35_ipd,
            BIn(0)  => B0_ipd,
            BIn(1)  => B1_ipd,
            BIn(2)  => B2_ipd,
            BIn(3)  => B3_ipd,
            BIn(4)  => B4_ipd,
            BIn(5)  => B5_ipd,
            BIn(6)  => B6_ipd,
            BIn(7)  => B7_ipd,
            BIn(8)  => B8_ipd,
            BIn(9)  => B9_ipd,
            BIn(10) => B10_ipd,
            BIn(11) => B11_ipd,
            BIn(12) => B12_ipd,
            BIn(13) => B13_ipd,
            BIn(14) => B14_ipd,
            BIn(15) => B15_ipd,
            BIn(16) => B16_ipd,
            BIn(17) => B17_ipd,
            BIn(18) => B18_ipd,
            BIn(19) => B19_ipd,
            BIn(20) => B20_ipd,
            BIn(21) => B21_ipd,
            BIn(22) => B22_ipd,
            BIn(23) => B23_ipd,
            BIn(24) => B24_ipd,
            BIn(25) => B25_ipd,
            BIn(26) => B26_ipd,
            BIn(27) => B27_ipd,
            BIn(28) => B28_ipd,
            BIn(29) => B29_ipd,
            BIn(30) => B30_ipd,
            BIn(31) => B31_ipd,
            BIn(32) => B32_ipd,
            BIn(33) => B33_ipd,
            BIn(34) => B34_ipd,
            BIn(35) => B35_ipd,
            AOut(0)  => A0,
            AOut(1)  => A1,
            AOut(2)  => A2,
            AOut(3)  => A3,
            AOut(4)  => A4,
            AOut(5)  => A5,
            AOut(6)  => A6,
            AOut(7)  => A7,
            AOut(8)  => A8,
            AOut(9)  => A9,
            AOut(10) => A10,
            AOut(11) => A11,
            AOut(12) => A12,
            AOut(13) => A13,
            AOut(14) => A14,
            AOut(15) => A15,
            AOut(16) => A16,
            AOut(17) => A17,
            AOut(18) => A18,
            AOut(19) => A19,
            AOut(20) => A20,
            AOut(21) => A21,
            AOut(22) => A22,
            AOut(23) => A23,
            AOut(24) => A24,
            AOut(25) => A25,
            AOut(26) => A26,
            AOut(27) => A27,
            AOut(28) => A28,
            AOut(29) => A29,
            AOut(30) => A30,
            AOut(31) => A31,
            AOut(32) => A32,
            AOut(33) => A33,
            AOut(34) => A34,
            AOut(35) => A35,
            BOut(0)  => B0,
            BOut(1)  => B1,
            BOut(2)  => B2,
            BOut(3)  => B3,
            BOut(4)  => B4,
            BOut(5)  => B5,
            BOut(6)  => B6,
            BOut(7)  => B7,
            BOut(8)  => B8,
            BOut(9)  => B9,
            BOut(10) => B10,
            BOut(11) => B11,
            BOut(12) => B12,
            BOut(13) => B13,
            BOut(14) => B14,
            BOut(15) => B15,
            BOut(16) => B16,
            BOut(17) => B17,
            BOut(18) => B18,
            BOut(19) => B19,
            BOut(20) => B20,
            BOut(21) => B21,
            BOut(22) => B22,
            BOut(23) => B23,
            BOut(24) => B24,
            BOut(25) => B25,
            BOut(26) => B26,
            BOut(27) => B27,
            BOut(28) => B28,
            BOut(29) => B29,
            BOut(30) => B30,
            BOut(31) => B31,
            BOut(32) => B32,
            BOut(33) => B33,
            BOut(34) => B34,
            BOut(35) => B35,
            AENeg    => AENeg,
            AFNeg    => AFNeg,
            EFNeg    => EFNeg,
            FFNeg    => FFNeg,
            MBF1Neg  => MBF1Neg,
            MBF2Neg  => MBF2Neg,
            PEFANeg  => PEFANeg,
            PEFBNeg  => PEFBNeg
      );
        SIGNAL AOut_zd    :std_logic_vector(HiDbit DOWNTO 0):=(OTHERS => 'U');
        SIGNAL BOut_zd    :std_logic_vector(HiDbit DOWNTO 0):=(OTHERS => 'U');
        SIGNAL AENeg_zd   : std_ulogic := 'U';
        SIGNAL AFNeg_zd   : std_ulogic := 'U';
        SIGNAL EFNeg_zd   : std_ulogic := 'U';
        SIGNAL FFNeg_zd   : std_ulogic := 'U';
        SIGNAL MBF1Neg_zd : std_ulogic := 'U';
        SIGNAL MBF2Neg_zd : std_ulogic := 'U';
        SIGNAL PEFANeg_zd : std_ulogic := 'U';
        SIGNAL PEFBNeg_zd : std_ulogic := 'U';
        SIGNAL MAIL1      :std_logic_vector(35 DOWNTO 0):=(OTHERS => 'U');
        SIGNAL MAIL2      :std_logic_vector(35 DOWNTO 0):=(OTHERS => 'U');

        -- Violation variable
        SIGNAL Viol         : X01 := '0';
        CONSTANT partID     : STRING := "idt723611L20";
        SIGNAL  flagCLKAskew2     : std_ulogic := '0';
        SIGNAL  flagCLKAskew1     : std_ulogic := '0';
        SIGNAL  flagCLKBskew2     : std_ulogic := '0';
        SIGNAL  flagCLKBskew1     : std_ulogic := '0';
        SIGNAL  INTER_AE          : INTEGER   := 5;
        SIGNAL  INTER_AF          : INTEGER   := 5;
        SIGNAL  INTER_FF          : INTEGER   := 5;
        SIGNAL  INTER_EF          : INTEGER   := 5;
        SIGNAL  OffsetRegister   : INTEGER    := 0;
        CONSTANT MaxData        : NATURAL := 16#3FFFF#;
        CONSTANT FIFOMemorySize : NATURAL :=64;
           -- Memory array declaration