📄 idt723611.vhd
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A5 : INOUT std_logic ; A6 : INOUT std_logic ; A7 : INOUT std_logic ; A8 : INOUT std_logic ; A9 : INOUT std_logic ; A10 : INOUT std_logic ; A11 : INOUT std_logic ; A12 : INOUT std_logic ; A13 : INOUT std_logic ; A14 : INOUT std_logic ; A15 : INOUT std_logic ; A16 : INOUT std_logic ; A17 : INOUT std_logic ; A18 : INOUT std_logic ; A19 : INOUT std_logic ; A20 : INOUT std_logic ; A21 : INOUT std_logic ; A22 : INOUT std_logic ; A23 : INOUT std_logic ; A24 : INOUT std_logic ; A25 : INOUT std_logic ; A26 : INOUT std_logic ; A27 : INOUT std_logic ; A28 : INOUT std_logic ; A29 : INOUT std_logic ; A30 : INOUT std_logic ; A31 : INOUT std_logic ; A32 : INOUT std_logic ; A33 : INOUT std_logic ; A34 : INOUT std_logic ; A35 : INOUT std_logic ; -- Data Input/Output Bus port B B0 : INOUT std_logic ; B1 : INOUT std_logic ; B2 : INOUT std_logic ; B3 : INOUT std_logic ; B4 : INOUT std_logic ; B5 : INOUT std_logic ; B6 : INOUT std_logic ; B7 : INOUT std_logic ; B8 : INOUT std_logic ; B9 : INOUT std_logic ; B10 : INOUT std_logic ; B11 : INOUT std_logic ; B12 : INOUT std_logic ; B13 : INOUT std_logic ; B14 : INOUT std_logic ; B15 : INOUT std_logic ; B16 : INOUT std_logic ; B17 : INOUT std_logic ; B18 : INOUT std_logic ; B19 : INOUT std_logic ; B20 : INOUT std_logic ; B21 : INOUT std_logic ; B22 : INOUT std_logic ; B23 : INOUT std_logic ; B24 : INOUT std_logic ; B25 : INOUT std_logic ; B26 : INOUT std_logic ; B27 : INOUT std_logic ; B28 : INOUT std_logic ; B29 : INOUT std_logic ; B30 : INOUT std_logic ; B31 : INOUT std_logic ; B32 : INOUT std_logic ; B33 : INOUT std_logic ; B34 : INOUT std_logic ; B35 : INOUT std_logic ; -- Almost-Empty Flag AENeg : OUT std_ulogic := 'U'; -- Almost-Full Flag AFNeg : OUT std_ulogic := 'U'; -- Empty Flag EFNeg : OUT std_ulogic := 'U'; -- Full Flag FFNeg : OUT std_ulogic := 'U'; -- Mail Register Flag MBF1Neg : OUT std_ulogic := 'U'; MBF2Neg : OUT std_ulogic := 'U'; -- Parity Error Flag PEFANeg : OUT std_ulogic := 'U'; PEFBNeg : OUT std_ulogic := 'U' ); ATTRIBUTE vital_level0 OF idt723611 : ENTITY IS True;END idt723611;--------------------------------------------------------------------------------- ARCHITECTURE DECLARATION-------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral of idt723611 IS ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE; CONSTANT partID : STRING := "idt723611"; CONSTANT MaxDataP : NATURAL := 16#3FFFF#; CONSTANT TotalLOC : NATURAL := 63; CONSTANT HiDbit : NATURAL := 35; CONSTANT DataWidth : NATURAL := 36; CONSTANT UserPreload : BOOLEAN := TRUE; SIGNAL CLKA_ipd : std_ulogic := 'U'; SIGNAL CLKB_ipd : std_ulogic := 'U'; -- Chip Select SIGNAL CSANeg_ipd : std_ulogic := 'U'; SIGNAL CSBNeg_ipd : std_ulogic := 'U'; -- Enable SIGNAL ENA_ipd : std_ulogic := 'U'; SIGNAL ENB_ipd : std_ulogic := 'U'; -- Flag-Offset Select SIGNAL FS0_ipd : std_ulogic := 'U'; SIGNAL FS1_ipd : std_ulogic := 'U'; -- Mailbox Select SIGNAL MBA_ipd : std_ulogic := 'U'; SIGNAL MBB_ipd : std_ulogic := 'U'; -- Odd/EvanParity Select SIGNAL OddEVENNeg_ipd : std_ulogic := 'U'; -- Parity Generation SIGNAL PGA_ipd : std_ulogic := 'U'; SIGNAL PGB_ipd : std_ulogic := 'U'; -- Reset SIGNAL RSTNeg_ipd : std_ulogic := 'U'; -- Write/Read Select SIGNAL WRANeg_ipd : std_ulogic := 'U'; SIGNAL WRBNeg_ipd : std_ulogic := 'U'; -- Data Input/Output Bus Port A SIGNAL A0_ipd : std_logic := 'U'; SIGNAL A1_ipd : std_logic := 'U'; SIGNAL A2_ipd : std_logic := 'U'; SIGNAL A3_ipd : std_logic := 'U'; SIGNAL A4_ipd : std_logic := 'U'; SIGNAL A5_ipd : std_logic := 'U'; SIGNAL A6_ipd : std_logic := 'U'; SIGNAL A7_ipd : std_logic := 'U'; SIGNAL A8_ipd : std_logic := 'U'; SIGNAL A9_ipd : std_logic := 'U'; SIGNAL A10_ipd : std_logic := 'U'; SIGNAL A11_ipd : std_logic := 'U'; SIGNAL A12_ipd : std_logic := 'U'; SIGNAL A13_ipd : std_logic := 'U'; SIGNAL A14_ipd : std_logic := 'U'; SIGNAL A15_ipd : std_logic := 'U'; SIGNAL A16_ipd : std_logic := 'U'; SIGNAL A17_ipd : std_logic := 'U'; SIGNAL A18_ipd : std_logic := 'U'; SIGNAL A19_ipd : std_logic := 'U'; SIGNAL A20_ipd : std_logic := 'U'; SIGNAL A21_ipd : std_logic := 'U'; SIGNAL A22_ipd : std_logic := 'U'; SIGNAL A23_ipd : std_logic := 'U'; SIGNAL A24_ipd : std_logic := 'U'; SIGNAL A25_ipd : std_logic := 'U'; SIGNAL A26_ipd : std_logic := 'U'; SIGNAL A27_ipd : std_logic := 'U'; SIGNAL A28_ipd : std_logic := 'U'; SIGNAL A29_ipd : std_logic := 'U'; SIGNAL A30_ipd : std_logic := 'U'; SIGNAL A31_ipd : std_logic := 'U'; SIGNAL A32_ipd : std_logic := 'U'; SIGNAL A33_ipd : std_logic := 'U'; SIGNAL A34_ipd : std_logic := 'U'; SIGNAL A35_ipd : std_logic := 'U';-- Data Input/Output Bus of Port B SIGNAL B0_ipd : std_logic := 'U'; SIGNAL B1_ipd : std_logic := 'U'; SIGNAL B2_ipd : std_logic := 'U'; SIGNAL B3_ipd : std_logic := 'U'; SIGNAL B4_ipd : std_logic := 'U'; SIGNAL B5_ipd : std_logic := 'U'; SIGNAL B6_ipd : std_logic := 'U'; SIGNAL B7_ipd : std_logic := 'U'; SIGNAL B8_ipd : std_logic := 'U'; SIGNAL B9_ipd : std_logic := 'U'; SIGNAL B10_ipd : std_logic := 'U'; SIGNAL B11_ipd : std_logic := 'U'; SIGNAL B12_ipd : std_logic := 'U'; SIGNAL B13_ipd : std_logic := 'U'; SIGNAL B14_ipd : std_logic := 'U'; SIGNAL B15_ipd : std_logic := 'U'; SIGNAL B16_ipd : std_logic := 'U'; SIGNAL B17_ipd : std_logic := 'U'; SIGNAL B18_ipd : std_logic := 'U'; SIGNAL B19_ipd : std_logic := 'U'; SIGNAL B20_ipd : std_logic := 'U'; SIGNAL B21_ipd : std_logic := 'U'; SIGNAL B22_ipd : std_logic := 'U'; SIGNAL B23_ipd : std_logic := 'U'; SIGNAL B24_ipd : std_logic := 'U'; SIGNAL B25_ipd : std_logic := 'U'; SIGNAL B26_ipd : std_logic := 'U'; SIGNAL B27_ipd : std_logic := 'U'; SIGNAL B28_ipd : std_logic := 'U'; SIGNAL B29_ipd : std_logic := 'U'; SIGNAL B30_ipd : std_logic := 'U'; SIGNAL B31_ipd : std_logic := 'U'; SIGNAL B32_ipd : std_logic := 'U'; SIGNAL B33_ipd : std_logic := 'U'; SIGNAL B34_ipd : std_logic := 'U'; SIGNAL B35_ipd : std_logic := 'U'; -- SKEW stuff (see also generics list) ALIAS tSKEW1 : VitalDelayType IS tdevice_SKEW1; ALIAS tSKEW2 : VitalDelayType IS tdevice_SKEW2; SIGNAL OpenIn, OpenOut : std_logic; BEGIN---------------------------------------------------------------------------------- Dummy instances for exporting tSKEW vals from SDF file-- using DEVICE construct-------------------------------------------------------------------------------- SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1)); SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2));------------------------------------------------------------------------------ Wire Delays---------------------------------------------------------------------------- WireDelay : BLOCK BEGIN w_1 : VitalWireDelay ( CLKA_ipd ,CLKA ,tipd_CLKA ); w_2 : VitalWireDelay ( CLKB_ipd ,CLKB ,tipd_CLKB ); w_3 : VitalWireDelay ( CSANeg_ipd ,CSANeg ,tipd_CSANeg); w_4 : VitalWireDelay ( CSBNeg_ipd ,CSBNeg ,tipd_CSBNeg); w_5 : VitalWireDelay ( ENA_ipd ,ENA ,tipd_ENA ); w_6 : VitalWireDelay ( ENB_ipd ,ENB ,tipd_ENB ); w_7 : VitalWireDelay ( FS0_ipd ,FS0 ,tipd_FS0 ); w_8 : VitalWireDelay ( FS1_ipd ,FS1 ,tipd_FS1 ); w_9 : VitalWireDelay ( MBA_ipd ,MBA ,tipd_MBA ); w_10 : VitalWireDelay ( MBB_ipd ,MBB ,tipd_MBB ); w_11 : VitalWireDelay ( OddEVENNeg_ipd ,OddEVENNeg ,tipd_OddEVENNeg); w_12 : VitalWireDelay ( PGA_ipd ,PGA ,tipd_PGA ); w_13 : VitalWireDelay ( PGB_ipd ,PGB ,tipd_PGB ); w_14 : VitalWireDelay ( RSTNeg_ipd ,RSTNeg ,tipd_RSTNeg ); w_15 : VitalWireDelay ( WRANeg_ipd ,WRANeg ,tipd_WRANeg ); w_16 : VitalWireDelay ( WRBNeg_ipd ,WRBNeg ,tipd_WRBNeg ); w_17 : VitalWireDelay ( A0_ipd ,A0 ,tipd_A0 ); w_18 : VitalWireDelay ( A1_ipd ,A1 ,tipd_A1 ); w_19 : VitalWireDelay ( A2_ipd ,A2 ,tipd_A2 ); w_20 : VitalWireDelay ( A3_ipd ,A3 ,tipd_A3 ); w_21 : VitalWireDelay ( A4_ipd ,A4 ,tipd_A4 ); w_22 : VitalWireDelay ( A5_ipd ,A5 ,tipd_A5 ); w_23 : VitalWireDelay ( A6_ipd ,A6 ,tipd_A6 ); w_24 : VitalWireDelay ( A7_ipd ,A7 ,tipd_A7 ); w_25 : VitalWireDelay ( A8_ipd ,A8 ,tipd_A8 ); w_26 : VitalWireDelay ( A9_ipd ,A9 ,tipd_A9 ); w_27 : VitalWireDelay ( A10_ipd ,A10 ,tipd_A10); w_28 : VitalWireDelay ( A11_ipd ,A11 ,tipd_A11); w_29 : VitalWireDelay ( A12_ipd ,A12 ,tipd_A12); w_30 : VitalWireDelay ( A13_ipd ,A13 ,tipd_A13); w_31 : VitalWireDelay ( A14_ipd ,A14 ,tipd_A14); w_32 : VitalWireDelay ( A15_ipd ,A15 ,tipd_A15); w_33 : VitalWireDelay ( A16_ipd ,A16 ,tipd_A16); w_34 : VitalWireDelay ( A17_ipd ,A17 ,tipd_A17); w_35 : VitalWireDelay ( A18_ipd ,A18 ,tipd_A18); w_36 : VitalWireDelay ( A19_ipd ,A19 ,tipd_A19); w_37 : VitalWireDelay ( A20_ipd ,A20 ,tipd_A20); w_38 : VitalWireDelay ( A21_ipd ,A21 ,tipd_A21); w_39 : VitalWireDelay ( A22_ipd ,A22 ,tipd_A22); w_40 : VitalWireDelay ( A23_ipd ,A23 ,tipd_A23); w_41 : VitalWireDelay ( A24_ipd ,A24 ,tipd_A24); w_42 : VitalWireDelay ( A25_ipd ,A25 ,tipd_A25); w_43 : VitalWireDelay ( A26_ipd ,A26 ,tipd_A26); w_44 : VitalWireDelay ( A27_ipd ,A27 ,tipd_A27); w_45 : VitalWireDelay ( A28_ipd ,A28 ,tipd_A28); w_46 : VitalWireDelay ( A29_ipd ,A29 ,tipd_A29); w_47 : VitalWireDelay ( A30_ipd ,A30 ,tipd_A30); w_48 : VitalWireDelay ( A31_ipd ,A31 ,tipd_A31); w_49 : VitalWireDelay ( A32_ipd ,A32 ,tipd_A32); w_50 : VitalWireDelay ( A33_ipd ,A33 ,tipd_A33); w_51 : VitalWireDelay ( A34_ipd ,A34 ,tipd_A34);⌨️ 快捷键说明
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