📄 idt723611.vhd
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---------------------------------------------------------------------------------- File Name: idt723611.vhd---------------------------------------------------------------------------------- Copyright (C) 2005 Free Model Foundry; http://www.freemodelfoundry.com/---- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.---- MODIFICATION HISTORY:---- version: | author: | mod date: | changes made:-- 2.0 O.Jankovic 05 Dec 12 full rewrite------------------------------------------------------------------------------------ PART DESCRIPTION:---- Library: FLASH MEMORY-- Technology: CMOS-- Part: IDT723611---- Description: 64 x 36 High-speed Fifo----------------------------------------------------------------------------------LIBRARY ieee; USE ieee.vital_primitives.ALL; USE ieee.vital_timing.ALL; USE ieee.std_logic_1164.ALL;LIBRARY fmf; USE fmf.gen_utils.ALL; USE fmf.conversions.to_nat; USE fmf.conversions.to_slv;--------------------------------------------------------------------------------- ENTITY DECLARATION-------------------------------------------------------------------------------ENTITY idt723611 IS GENERIC ( -- tipd delays: interconnect path delays -- generic control parameters -- Clock tipd_CLKA : VitalDelayType01 := VitalZeroDelay01; tipd_CLKB : VitalDelayType01 := VitalZeroDelay01; -- Chip Select tipd_CSANeg : VitalDelayType01 := VitalZeroDelay01; tipd_CSBNeg : VitalDelayType01 := VitalZeroDelay01; -- Enable tipd_ENA : VitalDelayType01 := VitalZeroDelay01; tipd_ENB : VitalDelayType01 := VitalZeroDelay01; -- Flag-Offset Select tipd_FS0 : VitalDelayType01 := VitalZeroDelay01; tipd_FS1 : VitalDelayType01 := VitalZeroDelay01; -- Mailbox Select tipd_MBA : VitalDelayType01 := VitalZeroDelay01; tipd_MBB : VitalDelayType01 := VitalZeroDelay01; -- Odd/EvanParity Select tipd_OddEVENNeg : VitalDelayType01 := VitalZeroDelay01; -- Parity Generation tipd_PGA : VitalDelayType01 := VitalZeroDelay01; tipd_PGB : VitalDelayType01 := VitalZeroDelay01; -- Reset tipd_RSTNeg : VitalDelayType01 := VitalZeroDelay01; -- Write/Read Select tipd_WRANeg : VitalDelayType01 := VitalZeroDelay01; tipd_WRBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5 : VitalDelayType01 := VitalZeroDelay01; tipd_A6 : VitalDelayType01 := VitalZeroDelay01; tipd_A7 : VitalDelayType01 := VitalZeroDelay01; tipd_A8 : VitalDelayType01 := VitalZeroDelay01; tipd_A9 : VitalDelayType01 := VitalZeroDelay01; tipd_A10 : VitalDelayType01 := VitalZeroDelay01; tipd_A11 : VitalDelayType01 := VitalZeroDelay01; tipd_A12 : VitalDelayType01 := VitalZeroDelay01; tipd_A13 : VitalDelayType01 := VitalZeroDelay01; tipd_A14 : VitalDelayType01 := VitalZeroDelay01; tipd_A15 : VitalDelayType01 := VitalZeroDelay01; tipd_A16 : VitalDelayType01 := VitalZeroDelay01; tipd_A17 : VitalDelayType01 := VitalZeroDelay01; tipd_A18 : VitalDelayType01 := VitalZeroDelay01; tipd_A19 : VitalDelayType01 := VitalZeroDelay01; tipd_A20 : VitalDelayType01 := VitalZeroDelay01; tipd_A21 : VitalDelayType01 := VitalZeroDelay01; tipd_A22 : VitalDelayType01 := VitalZeroDelay01; tipd_A23 : VitalDelayType01 := VitalZeroDelay01; tipd_A24 : VitalDelayType01 := VitalZeroDelay01; tipd_A25 : VitalDelayType01 := VitalZeroDelay01; tipd_A26 : VitalDelayType01 := VitalZeroDelay01; tipd_A27 : VitalDelayType01 := VitalZeroDelay01; tipd_A28 : VitalDelayType01 := VitalZeroDelay01; tipd_A29 : VitalDelayType01 := VitalZeroDelay01; tipd_A30 : VitalDelayType01 := VitalZeroDelay01; tipd_A31 : VitalDelayType01 := VitalZeroDelay01; tipd_A32 : VitalDelayType01 := VitalZeroDelay01; tipd_A33 : VitalDelayType01 := VitalZeroDelay01; tipd_A34 : VitalDelayType01 := VitalZeroDelay01; tipd_A35 : VitalDelayType01 := VitalZeroDelay01; tipd_B0 : VitalDelayType01 := VitalZeroDelay01; tipd_B1 : VitalDelayType01 := VitalZeroDelay01; tipd_B2 : VitalDelayType01 := VitalZeroDelay01; tipd_B3 : VitalDelayType01 := VitalZeroDelay01; tipd_B4 : VitalDelayType01 := VitalZeroDelay01; tipd_B5 : VitalDelayType01 := VitalZeroDelay01; tipd_B6 : VitalDelayType01 := VitalZeroDelay01; tipd_B7 : VitalDelayType01 := VitalZeroDelay01; tipd_B8 : VitalDelayType01 := VitalZeroDelay01; tipd_B9 : VitalDelayType01 := VitalZeroDelay01; tipd_B10 : VitalDelayType01 := VitalZeroDelay01; tipd_B11 : VitalDelayType01 := VitalZeroDelay01; tipd_B12 : VitalDelayType01 := VitalZeroDelay01; tipd_B13 : VitalDelayType01 := VitalZeroDelay01; tipd_B14 : VitalDelayType01 := VitalZeroDelay01; tipd_B15 : VitalDelayType01 := VitalZeroDelay01; tipd_B16 : VitalDelayType01 := VitalZeroDelay01; tipd_B17 : VitalDelayType01 := VitalZeroDelay01; tipd_B18 : VitalDelayType01 := VitalZeroDelay01; tipd_B19 : VitalDelayType01 := VitalZeroDelay01; tipd_B20 : VitalDelayType01 := VitalZeroDelay01; tipd_B21 : VitalDelayType01 := VitalZeroDelay01; tipd_B22 : VitalDelayType01 := VitalZeroDelay01; tipd_B23 : VitalDelayType01 := VitalZeroDelay01; tipd_B24 : VitalDelayType01 := VitalZeroDelay01; tipd_B25 : VitalDelayType01 := VitalZeroDelay01; tipd_B26 : VitalDelayType01 := VitalZeroDelay01; tipd_B27 : VitalDelayType01 := VitalZeroDelay01; tipd_B28 : VitalDelayType01 := VitalZeroDelay01; tipd_B29 : VitalDelayType01 := VitalZeroDelay01; tipd_B30 : VitalDelayType01 := VitalZeroDelay01; tipd_B31 : VitalDelayType01 := VitalZeroDelay01; tipd_B32 : VitalDelayType01 := VitalZeroDelay01; tipd_B33 : VitalDelayType01 := VitalZeroDelay01; tipd_B34 : VitalDelayType01 := VitalZeroDelay01; tipd_B35 : VitalDelayType01 := VitalZeroDelay01;-- tpd_ tpd_CLKB_B0 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_MBB_B0 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_CSANeg_A0 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_WRANeg_A0 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_CSBNeg_B0 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_WRBNeg_B0 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_CLKA_B0_READMAIL1_EQ_1 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_CLKB_A0_READMAIL2_EQ_1 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_ODDEVENNeg_A0_READMAIL2_EQ_1 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_ODDEVENNeg_B0_READMAIL1_EQ_1 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_CSANeg_A0_READMAIL2_EQ_1 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_CSBNeg_B0_READMAIL1_EQ_1 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_ENA_A0_READMAIL2_EQ_1 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_ENB_B0_READMAIL1_EQ_1 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_WRANeg_A0_READMAIL2_EQ_1 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_WRBNeg_B0_READMAIL1_EQ_1 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_MBA_A0_READMAIL2_EQ_1 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_MBB_B0_READMAIL1_EQ_1 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_PGA_A0_READMAIL2_EQ_1 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_PGB_B0_READMAIL1_EQ_1 : VitalDelayType01Z := VitalZeroDelay01Z; tpd_CLKA_FFNeg : VitalDelayType01 := VitalZeroDelay01; tpd_CLKB_EFNeg : VitalDelayType01 := VitalZeroDelay01; tpd_CLKB_AENeg : VitalDelayType01 := VitalZeroDelay01; tpd_CLKA_AFNeg : VitalDelayType01 := VitalZeroDelay01; tpd_CLKA_MBF1Neg : VitalDelayType01 := VitalZeroDelay01; tpd_CLKA_MBF2Neg : VitalDelayType01 := VitalZeroDelay01; tpd_CLKB_MBF1Neg : VitalDelayType01 := VitalZeroDelay01; tpd_CLKB_MBF2Neg : VitalDelayType01 := VitalZeroDelay01; tpd_A0_PEFANeg : VitalDelayType01 := VitalZeroDelay01; tpd_B0_PEFBNeg : VitalDelayType01 := VitalZeroDelay01; tpd_OddEVENNeg_PEFANeg : VitalDelayType01 := VitalZeroDelay01; tpd_OddEVENNeg_PEFBNeg : VitalDelayType01 := VitalZeroDelay01; tpd_CSANeg_PEFANeg : VitalDelayType01 := VitalZeroDelay01; tpd_ENA_PEFANeg : VitalDelayType01 := VitalZeroDelay01; tpd_WRANeg_PEFANeg : VitalDelayType01 := VitalZeroDelay01; tpd_MBA_PEFANeg : VitalDelayType01 := VitalZeroDelay01; tpd_PGA_PEFANeg : VitalDelayType01 := VitalZeroDelay01; tpd_CSBNeg_PEFBNeg : VitalDelayType01 := VitalZeroDelay01; tpd_ENB_PEFBNeg : VitalDelayType01 := VitalZeroDelay01; tpd_WRBNeg_PEFBNeg : VitalDelayType01 := VitalZeroDelay01; tpd_MBB_PEFBNeg : VitalDelayType01 := VitalZeroDelay01; tpd_PGB_PEFBNeg : VitalDelayType01 := VitalZeroDelay01; tpd_RSTNeg_AENeg : VitalDelayType01 := VitalZeroDelay01; tpd_RSTNeg_AFNeg : VitalDelayType01 := VitalZeroDelay01; tpd_RSTNeg_MBF1Neg : VitalDelayType01 := VitalZeroDelay01; tpd_RSTNeg_MBF2Neg : VitalDelayType01 := VitalZeroDelay01;-- tsetup values: setup times tsetup_A0_CLKA : VitalDelayType := UnitDelay; tsetup_CSANeg_CLKA : VitalDelayType := UnitDelay; tsetup_ENA_CLKA : VitalDelayType := UnitDelay; tsetup_MBA_CLKA : VitalDelayType := UnitDelay; tsetup_OddEVENNeg_CLKB : VitalDelayType := UnitDelay; tsetup_PGB_CLKB : VitalDelayType := UnitDelay; tsetup_RSTNeg_CLKA : VitalDelayType := UnitDelay; tsetup_FS0_RSTNeg : VitalDelayType := UnitDelay; -- thold values: hold times thold_A0_CLKA : VitalDelayType := UnitDelay; thold_CSANeg_CLKA : VitalDelayType := UnitDelay; thold_ENA_CLKA : VitalDelayType := UnitDelay; thold_MBA_CLKA : VitalDelayType := UnitDelay; thold_OddEVENNeg_CLKB : VitalDelayType := UnitDelay; thold_RSTNeg_CLKA : VitalDelayType := UnitDelay; thold_FS0_RSTNeg : VitalDelayType := UnitDelay; -- pulse width tpw_CLKA_negedge : VitalDelayType := UnitDelay; tpw_CLKA_posedge : VitalDelayType := UnitDelay; tpw_CLKB_negedge : VitalDelayType := UnitDelay; tpw_CLKB_posedge : VitalDelayType := UnitDelay; -- tperiod values tperiod_CLKA : VitalDelayType := UnitDelay; tperiod_CLKB : VitalDelayType := UnitDelay; -- tSKEW1 (skew time) tdevice_SKEW1 : VitalDelayType := UnitDelay;-- tSKEW2 (skew time) tdevice_SKEW2 : VitalDelayType := UnitDelay; InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := true; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; TimingModel : STRING :="idt723611L20"); PORT ( -- Clock CLKA : IN std_logic := 'U'; CLKB : IN std_logic := 'U'; -- Chip Select CSANeg : IN std_logic := 'U'; CSBNeg : IN std_logic := 'U'; -- Enable ENA : IN std_logic := 'U'; ENB : IN std_logic := 'U'; -- Flag-Offset Select FS0 : IN std_logic := 'U'; FS1 : IN std_logic := 'U'; -- Mailbox Select MBA : IN std_logic := 'U'; MBB : IN std_logic := 'U'; -- Odd/EvanParity Select OddEVENNeg : IN std_ulogic := 'U'; -- Parity Generation PGA : IN std_ulogic := 'U'; PGB : IN std_ulogic := 'U'; -- Reset RSTNeg : IN std_ulogic := 'U'; -- Write/Read Select WRANeg : IN std_ulogic := 'U'; WRBNeg : IN std_ulogic := 'U'; -- Data Input/Output Bus port A A0 : INOUT std_logic ; A1 : INOUT std_logic ; A2 : INOUT std_logic ; A3 : INOUT std_logic ; A4 : INOUT std_logic ;⌨️ 快捷键说明
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