idt7200.vhd

VHDL的ram和fifo model code 包含众多的厂家

                    XONeg_zd := '1';
                END IF;
                IF Count = TotalLoc THEN
                    FFNeg_zd := '0';
                ELSE
                    FFNeg_zd := '1';
                END IF;
                IF EFNeg_zd = '0' AND RNeg_nwv = '0' THEN
                    DataDrive := To_X01(DIn);
                    EF_pzd := '1';
                    Count := Count - 1;
                    RDPoint := RDPoint + 1;
                END IF;
                EFNeg_zd := '1';
            ELSE
                IF mode /= single THEN
                    XONeg_zd := '1';
                END IF;
            END IF;
        ELSIF falling_edge(WNegIn) AND mode /= single AND Count = TotalLoc THEN
            XONeg_zd := '0';
            wr_stat := inact;
        END IF;

        IF falling_edge(RNegIn) AND EFNeg_zd = '1' AND rd_stat = act THEN
            IF Violation = '0' THEN
                IF MemData(RDPoint) >= 0 THEN
                    DataDrive := To_slv(MemData(RDPoint), DataWidth);
                ELSE
                    DataDrive := (OTHERS => 'X');
                END IF;
            ELSE
                MemData(WRPoint) := -1;
            END IF;
            Count := Count - 1;
            IF Count > Half AND mode = single THEN
                XONeg_zd := '0';
            ELSE
                XONeg_zd := '1';
            END IF;
            IF Count = 0 THEN
                EFNeg_zd := '0';
                IF mode = other_exp THEN
                    XONeg_zd := '0';
                END IF;
            ELSE
                EFNeg_zd := '1';
            END IF;
            if RDPoint = WRPoint-1 then  -- We must increment RDPoint if it
                                         --  is the last element because...
                 IF RDPoint = TotalLoc THEN
                     RDPoint := 0;
                 ELSE
                     RDPoint := RDPoint + 1;
                 END IF;
             end if;
        ELSIF rising_edge(RNegIn) THEN
            IF EFNeg_zd = '1' AND rd_stat = act THEN
                IF FFNeg_zd = '0' AND WNeg_nwv = '0' THEN
                    FF_pzd := '1';
                END IF;
                FFNeg_zd := '1';
                IF RDPoint = TotalLoc THEN
                    RDPoint := 0;
                ELSE
                    RDPoint := RDPoint + 1;
                END IF;
            END IF;
            IF mode = other_exp AND Count = 0 THEN
                XONeg_zd := '1';
                rd_stat := inact;
            END IF;
        END IF;

        IF falling_edge(FLNegIn) AND XINeg_nwv = '0' THEN
            RDPoint := 0;
            Count := WRPoint;
            IF Count > Half THEN
                XONeg_zd := '0';
            ELSE
                XONeg_zd := '1';
            END IF;
            IF Count = 0 THEN
                EFNeg_zd := '0';
            ELSE
                EFNeg_zd := '1';
            END IF;
            IF Count = TotalLoc THEN
                FFNeg_zd := '0';
            ELSE
                FFNeg_zd := '1';
            END IF;
        ELSIF falling_edge(XINegIn) AND mode = other_exp THEN
            IF wr_stat = inact THEN
                wr_stat := act;
            ELSE
                rd_stat := act;
            END IF;
        END IF;

        IF rising_edge(EF_pulse) THEN
            EFNeg_zd := '0';
            EF_pulse <= '0';
        ELSIF rising_edge(FF_pulse) THEN
            FFNeg_zd := '0';
            FF_pulse <= '0';
        END IF;

        IF rising_edge(RNegIn) THEN
            DataDrive := (others => 'Z');
        END IF;

        Q_zd <= DataDrive;

        --------------------------------------------------------------------
        -- Path Delay Section
        --------------------------------------------------------------------
        VitalPathDelay01 (
            OutSignal       => EF_pulse,
            OutSignalName   => "EF_pulse",
            OutTemp         => EF_pzd,
            GlitchData      => EFp_GlitchData,
            XOn             => false,
            MsgOn           => false,
            Paths           => (
            0 => (InputChangeTime   => WNeg'LAST_EVENT,
                  PathDelay         => tpd_RNeg_EFNeg,
                  PathCondition     => true)
            )
        );

        VitalPathDelay01 (
            OutSignal       => FF_pulse,
            OutSignalName   => "FF_pulse",
            OutTemp         => FF_pzd,
            GlitchData      => FFp_GlitchData,
            XOn             => false,
            MsgOn           => false,
            Paths           => (
            0 => (InputChangeTime   => RNeg'LAST_EVENT,
                  PathDelay         => tpd_WNeg_FFNeg,
                  PathCondition     => true)
            )
        );

        VitalPathDelay01 (
            OutSignal       => EFNegOut,
            OutSignalName   => "EFNeg",
            OutTemp         => EFNeg_zd,
            GlitchData      => EFNeg_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
            0 => (InputChangeTime   => FLNeg'LAST_EVENT,
                  PathDelay         => tpd_FLNeg_EFNeg,
                  PathCondition     => FLNeg_nwv = '0'),
            1 => (InputChangeTime   => RNeg'LAST_EVENT,
                  PathDelay         => tpd_RNeg_EFNeg,
                  PathCondition     => true),
            2 => (InputChangeTime   => WNeg'LAST_EVENT,
                  PathDelay         => tpd_WNeg_EFNeg,
                  PathCondition     => true),
            3 => (InputChangeTime   => RSNeg'LAST_EVENT,
                  PathDelay         => tpd_RSNeg_EFNeg,
                  PathCondition     => true),
            4 => (InputChangeTime   => EF_pulse'LAST_EVENT,
                  PathDelay         => tpd_RNeg_EFNeg,
                  PathCondition     => true)
            )
        );

        VitalPathDelay01 (
            OutSignal       => FFNegOut,
            OutSignalName   => "FFNeg",
            OutTemp         => FFNeg_zd,
            GlitchData      => FFNeg_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
            0 => (InputChangeTime   => FLNeg'LAST_EVENT,
                  PathDelay         => tpd_FLNeg_EFNeg,
                  PathCondition     => FLNeg_nwv = '0'),
            1 => (InputChangeTime   => RNeg'LAST_EVENT,
                  PathDelay         => tpd_RNeg_FFNeg,
                  PathCondition     => true),
            2 => (InputChangeTime   => WNeg'LAST_EVENT,
                  PathDelay         => tpd_WNeg_FFNeg,
                  PathCondition     => true),
            3 => (InputChangeTime   => RSNeg'LAST_EVENT,
                  PathDelay         => tpd_RSNeg_FFNeg,
                  PathCondition     => true),
            4 => (InputChangeTime   => FF_pulse'LAST_EVENT,
                  PathDelay         => tpd_WNeg_EFNeg,
                  PathCondition     => true)
            )
        );

        VitalPathDelay01 (
            OutSignal       => XONegOut,
            OutSignalName   => "XONeg",
            OutTemp         => XONeg_zd,
            GlitchData      => XONeg_GlitchData,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Paths           => (
            0 => (InputChangeTime   => FLNeg'LAST_EVENT,
                  PathDelay         => tpd_FLNeg_EFNeg,
                  PathCondition     => FLNeg_nwv = '0'),
            1 => (InputChangeTime   => RNeg'LAST_EVENT,
                  PathDelay         => tpd_RNeg_XONeg,
                  PathCondition     => true),
            2 => (InputChangeTime   => WNeg'LAST_EVENT,
                  PathDelay         => tpd_WNeg_XONeg,
                  PathCondition     => true),
            3 => (InputChangeTime   => RSNeg'LAST_EVENT,
                  PathDelay         => tpd_RSNeg_XONeg,
                  PathCondition     => true)
            )
        );

        END PROCESS Fifo;

        ------------------------------------------------------------------------
        -- Path Delay Processes generated as a function of data width
        ------------------------------------------------------------------------
        DataOut_Width : FOR i IN HiDbit DOWNTO 0 GENERATE
            DataOut_Delay : PROCESS (Q_zd(i))
              VARIABLE Q_GlitchData:VitalGlitchDataArrayType(HiDbit Downto 0);
            BEGIN
                VitalPathDelay01Z (
                    OutSignal       => QOut(i),
                    OutSignalName   => "Q",
                    OutTemp         => Q_zd(i),
                    Mode            => VitalTransport,
                    GlitchData      => Q_GlitchData(i),
                    Paths           => (
                        0 => (InputChangeTime => RNegIn'LAST_EVENT,
                              PathDelay       => tpd_RNeg_Q0,
                              PathCondition   => TRUE),
                        1 => (InputChangeTime => WNegIn'LAST_EVENT,
                              PathDelay       => tpd_WNeg_Q0,
                              PathCondition   => TRUE)
                   )
               );
            END PROCESS;
        END GENERATE;

    END BLOCK;
END vhdl_behavioral;