idt7200.vhd

VHDL的ram和fifo model code 包含众多的厂家

--------------------------------------------------------------------------------
--  File Name: idt7200.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 2001 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0    R. Munden    01 Jan 20   Initial release
--    V1.1    D. Rambaud   01 Nov 10   fixed problem with RDPoint
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:    FIFO
--  Technology: CMOS
--  Part:       IDT7200
-- 
--  Description: Async FIFO 256 x 9
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.conversions.ALL;

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY idt7200 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_D0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D8                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_FLNeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_RNeg                : VitalDelayType01 := VitalZeroDelay01;
        tipd_RSNeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_WNeg                : VitalDelayType01 := VitalZeroDelay01;
        tipd_XINeg               : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_FLNeg_EFNeg          : VitalDelayType01 := UnitDelay01;
        tpd_RNeg_Q0              : VitalDelayType01Z := UnitDelay01Z;
        tpd_RNeg_EFNeg           : VitalDelayType01 := UnitDelay01;
        tpd_RNeg_FFNeg           : VitalDelayType01 := UnitDelay01;
        tpd_RNeg_XONeg           : VitalDelayType01 := UnitDelay01;
        tpd_RSNeg_EFNeg          : VitalDelayType01 := UnitDelay01;
        tpd_RSNeg_FFNeg          : VitalDelayType01 := UnitDelay01;
        tpd_RSNeg_XONeg          : VitalDelayType01 := UnitDelay01;
        tpd_WNeg_Q0              : VitalDelayType01Z := UnitDelay01Z;
        tpd_WNeg_EFNeg           : VitalDelayType01 := UnitDelay01;
        tpd_WNeg_FFNeg           : VitalDelayType01 := UnitDelay01;
        tpd_WNeg_XONeg           : VitalDelayType01 := UnitDelay01;
        -- tpw values: pulse widths
        tpw_RNeg_negedge         : VitalDelayType   := UnitDelay;
        tpw_RNeg_posedge         : VitalDelayType   := UnitDelay;
        tpw_WNeg_negedge         : VitalDelayType   := UnitDelay;
        tpw_WNeg_posedge         : VitalDelayType   := UnitDelay;
        tpw_RSNeg_negedge        : VitalDelayType   := UnitDelay;
        tpw_FLNeg_negedge        : VitalDelayType   := UnitDelay;
        tpw_FLNeg_posedge        : VitalDelayType   := UnitDelay;
        tpw_XINeg_negedge        : VitalDelayType   := UnitDelay;
        tpw_XINeg_posedge        : VitalDelayType   := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_RNeg             : VitalDelayType   := UnitDelay;
        tperiod_WNeg             : VitalDelayType   := UnitDelay;
        -- tsetup values: setup times
        tsetup_D0_WNeg           : VitalDelayType   := UnitDelay;
        tsetup_RNeg_RSNeg        : VitalDelayType   := UnitDelay;
        tsetup_RNeg_FLNeg        : VitalDelayType   := UnitDelay;
        tsetup_XINeg_RNeg        : VitalDelayType   := UnitDelay;
        -- thold values: hold times
        thold_D0_WNeg            : VitalDelayType   := UnitDelay;
        thold_RNeg_RSNeg         : VitalDelayType   := UnitDelay;
        thold_RNeg_FLNeg         : VitalDelayType   := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        D0              : IN    std_ulogic := 'U';
        D1              : IN    std_ulogic := 'U';
        D2              : IN    std_ulogic := 'U';
        D3              : IN    std_ulogic := 'U';
        D4              : IN    std_ulogic := 'U';
        D5              : IN    std_ulogic := 'U';
        D6              : IN    std_ulogic := 'U';
        D7              : IN    std_ulogic := 'U';
        D8              : IN    std_ulogic := 'U';
        Q0              : OUT   std_ulogic := 'U';
        Q1              : OUT   std_ulogic := 'U';
        Q2              : OUT   std_ulogic := 'U';
        Q3              : OUT   std_ulogic := 'U';
        Q4              : OUT   std_ulogic := 'U';
        Q5              : OUT   std_ulogic := 'U';
        Q6              : OUT   std_ulogic := 'U';
        Q7              : OUT   std_ulogic := 'U';
        Q8              : OUT   std_ulogic := 'U';
        EFNeg           : OUT   std_ulogic := 'U';
        FFNeg           : OUT   std_ulogic := 'U';
        FLNeg           : IN    std_ulogic := 'U';
        RNeg            : IN    std_ulogic := 'U';
        RSNeg           : IN    std_ulogic := 'U';
        WNeg            : IN    std_ulogic := 'U';
        XINeg           : IN    std_ulogic := 'U';
        XONeg           : OUT   std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of idt7200 : ENTITY IS TRUE;
END idt7200;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of idt7200 IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID         : STRING := "IDT7200";
    CONSTANT MaxData        : NATURAL := 511;
    CONSTANT TotalLOC       : NATURAL := 255;
    CONSTANT Half           : NATURAL := TotalLOC/2;
    CONSTANT DataWidth      : NATURAL := 9;
    CONSTANT HiDbit         : NATURAL := 8;

    SIGNAL D0_ipd              : std_ulogic := 'U';
    SIGNAL D1_ipd              : std_ulogic := 'U';
    SIGNAL D2_ipd              : std_ulogic := 'U';
    SIGNAL D3_ipd              : std_ulogic := 'U';
    SIGNAL D4_ipd              : std_ulogic := 'U';
    SIGNAL D5_ipd              : std_ulogic := 'U';
    SIGNAL D6_ipd              : std_ulogic := 'U';
    SIGNAL D7_ipd              : std_ulogic := 'U';
    SIGNAL D8_ipd              : std_ulogic := 'U';
    SIGNAL FLNeg_ipd           : std_ulogic := 'U';
    SIGNAL RNeg_ipd            : std_ulogic := 'U';
    SIGNAL RSNeg_ipd           : std_ulogic := 'U';
    SIGNAL WNeg_ipd            : std_ulogic := 'U';
    SIGNAL XINeg_ipd           : std_ulogic := 'U';

BEGIN

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (D0_ipd, D0, tipd_D0);
        w_2 : VitalWireDelay (D1_ipd, D1, tipd_D1);
        w_3 : VitalWireDelay (D2_ipd, D2, tipd_D2);
        w_4 : VitalWireDelay (D3_ipd, D3, tipd_D3);
        w_5 : VitalWireDelay (D4_ipd, D4, tipd_D4);
        w_6 : VitalWireDelay (D5_ipd, D5, tipd_D5);
        w_7 : VitalWireDelay (D6_ipd, D6, tipd_D6);
        w_8 : VitalWireDelay (D7_ipd, D7, tipd_D7);
        w_9 : VitalWireDelay (D8_ipd, D8, tipd_D8);
        w_21 : VitalWireDelay (FLNeg_ipd, FLNeg, tipd_FLNeg);
        w_22 : VitalWireDelay (RNeg_ipd, RNeg, tipd_RNeg);
        w_23 : VitalWireDelay (RSNeg_ipd, RSNeg, tipd_RSNeg);
        w_24 : VitalWireDelay (WNeg_ipd, WNeg, tipd_WNeg);
        w_25 : VitalWireDelay (XINeg_ipd, XINeg, tipd_XINeg);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            DIn      : IN    std_logic_vector(HiDbit downto 0);
            QOut     : OUT   std_logic_vector(HiDbit downto 0);
            FLNegIn  : IN    std_Ulogic := 'U';
            RNegIn   : IN    std_Ulogic := 'U';
            RSNegIn  : IN    std_Ulogic := 'U';
            WNegIn   : IN    std_Ulogic := 'U';
            XINegIn  : IN    std_Ulogic := 'U';
            EFNegOut : OUT   std_Ulogic := 'U';
            FFNegOut : OUT   std_Ulogic := 'U';
            XONegOut : OUT   std_Ulogic := 'U'
        );
        PORT MAP (
            DIn(0) => D0_ipd,
            DIn(1) => D1_ipd,
            DIn(2) => D2_ipd,
            DIn(3) => D3_ipd,
            DIn(4) => D4_ipd,
            DIn(5) => D5_ipd,
            DIn(6) => D6_ipd,
            DIn(7) => D7_ipd,
            DIn(8) => D8_ipd,
            QOut(0) => Q0,
            QOut(1) => Q1,
            QOut(2) => Q2,
            QOut(3) => Q3,
            QOut(4) => Q4,
            QOut(5) => Q5,
            QOut(6) => Q6,
            QOut(7) => Q7,
            QOut(8) => Q8,
            FLNegIn => FLNeg_ipd,
            RSNegIn => RSNeg_ipd,
            XINegIn => XINeg_ipd,
            RNegIn => RNeg_ipd,
            WNegIn => WNeg_ipd,
            EFNegOut => EFNeg,
            FFNegOut => FFNeg,
            XONegOut => XONeg
        );

    SIGNAL Q_zd : std_logic_vector(HiDbit downto 0) := (others => 'Z');
    SIGNAL EF_pulse : std_ulogic := '0';
    SIGNAL FF_pulse : std_ulogic := '0';

    BEGIN
        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Fifo : PROCESS (DIn, FLNegIn, RSNegIn, XINegIn, RNegIn, WNegIn,
                        EF_pulse, FF_pulse)

            -- Timing Check Variables
            VARIABLE Tviol_D0_WNeg         : X01 := '0';
            VARIABLE TD_D0_WNeg            : VitalTimingDataType;

            VARIABLE Tviol_RNeg_RSNeg      : X01 := '0';
            VARIABLE TD_RNeg_RSNeg         : VitalTimingDataType;

            VARIABLE Tviol_RNeg_FLNeg      : X01 := '0';
            VARIABLE TD_RNeg_FLNeg         : VitalTimingDataType;

            VARIABLE Tviol_XINeg_RNeg      : X01 := '0';
            VARIABLE TD_XINeg_RNeg         : VitalTimingDataType;

            VARIABLE Tviol_XINeg_WNeg      : X01 := '0';
            VARIABLE TD_XINeg_WNeg         : VitalTimingDataType;