idt723651.vhd

VHDL的ram和fifo model code 包含众多的厂家

    A(3)    	=> A3,
    A(4)        => A4,
    A(5)        => A5,
    A(6)        => A6,
    A(7)    	=> A7,
    A(8)    	=> A8,
    A(9)    	=> A9,
    A(10)   	=> A10,
    A(11)   	=> A11,
    A(12)   	=> A12,
    A(13)   	=> A13,
    A(14)   	=> A14,
    A(15)   	=> A15,
    A(16)   	=> A16,
    A(17)   	=> A17,
    A(18)   	=> A18,
    A(19)   	=> A19,
    A(20)   	=> A20,
    A(21)   	=> A21,
    A(22)   	=> A22,
    A(23)   	=> A23,
    A(24)   	=> A24,
    A(25)   	=> A25,
    A(26)   	=> A26,
    A(27)   	=> A27,
    A(28)   	=> A28,
    A(29)   	=> A29,
    A(30)   	=> A30,
    A(31)   	=> A31,
    A(32)   	=> A32,
    A(33)   	=> A33,
    A(34)   	=> A34,
    A(35)    	=> A35,
    AENeg  	    => AENeg,
    AFNeg   	=> AFNeg,
    B_ipd(0)    => B0_ipd,
    B_ipd(1)    => B1_ipd,
    B_ipd(2)    => B2_ipd,
    B_ipd(3)    => B3_ipd,
    B_ipd(4)    => B4_ipd,
    B_ipd(5)    => B5_ipd,
    B_ipd(6)    => B6_ipd,
    B_ipd(7)    => B7_ipd,
    B_ipd(8)    => B8_ipd,
    B_ipd(9)    => B9_ipd,
    B_ipd(10)   => B10_ipd,
    B_ipd(11)   => B11_ipd,
    B_ipd(12)   => B12_ipd,
    B_ipd(13)   => B13_ipd,
    B_ipd(14)   => B14_ipd,
    B_ipd(15)   => B15_ipd,
    B_ipd(16)   => B16_ipd,
    B_ipd(17)   => B17_ipd,
    B_ipd(18)   => B18_ipd,
    B_ipd(19)   => B19_ipd,
    B_ipd(20)   => B20_ipd,
    B_ipd(21)   => B21_ipd,
    B_ipd(22)   => B22_ipd,
    B_ipd(23)   => B23_ipd,
    B_ipd(24)   => B24_ipd,
    B_ipd(25)   => B25_ipd,
    B_ipd(26)   => B26_ipd,
    B_ipd(27)   => B27_ipd,
    B_ipd(28)   => B28_ipd,
    B_ipd(29)   => B29_ipd,
    B_ipd(30)   => B30_ipd,
    B_ipd(31)   => B31_ipd,
    B_ipd(32)   => B32_ipd,
    B_ipd(33)   => B33_ipd,
    B_ipd(34)   => B34_ipd,
    B_ipd(35)   => B35_ipd,
    B(0)    	=> B0,
    B(1)    	=> B1,
    B(2)    	=> B2,
    B(3)    	=> B3,
    B(4)        => B4,
    B(5)        => B5,
    B(6)        => B6,
    B(7)    	=> B7,
    B(8)    	=> B8,
    B(9)    	=> B9,
    B(10)   	=> B10,
    B(11)   	=> B11,
    B(12)   	=> B12,
    B(13)   	=> B13,
    B(14)   	=> B14,
    B(15)   	=> B15,
    B(16)   	=> B16,
    B(17)   	=> B17,
    B(18)   	=> B18,
    B(19)   	=> B19,
    B(20)   	=> B20,
    B(21)   	=> B21,
    B(22)   	=> B22,
    B(23)   	=> B23,
    B(24)   	=> B24,
    B(25)   	=> B25,
    B(26)   	=> B26,
    B(27)   	=> B27,
    B(28)   	=> B28,
    B(29)   	=> B29,
    B(30)   	=> B30,
    B(31)   	=> B31,
    B(32)   	=> B32,
    B(33)   	=> B33,
    B(34)   	=> B34,
    B(35)    	=> B35,

    CLKA        => CLKA_ipd,
    CLKB        => CLKB_ipd,
    CSANeg      => CSANeg_ipd,
    CSBNeg      => CSBNeg_ipd,
   
    ENA         => ENA_ipd,
    ENB         => ENB_ipd,
    IR          => IR,

    FS0SD       => FS0SD_ipd,
    FS1SEN      => FS1SEN_ipd,
    MBA         => MBA_ipd,
    MBB         => MBB_ipd,
    MBF1Neg     => MBF1Neg,
    MBF2Neg     => MBF2Neg,
    ORB         => ORB,
    RSTNeg      => RSTNeg_ipd,

    RFM         =>RFM_ipd,
    RTM         =>RTM_ipd,
    WRA         => WRA_ipd,
    WRB         => WRB_ipd);
    
  -- zero delayed outputs and bidirectional ports 
  -- (func. sec. uses these signals instead of =
  --  actual outputs and bidirectional ports);
  -- actual outputs are assigned in Path Delay Section
  
  SIGNAL A_zd         : std_logic_vector (35 downto 0);
  SIGNAL B_zd         : std_logic_vector (35 downto 0); 
  SIGNAL AENeg_zd     : std_logic; 
  SIGNAL AFNeg_zd     : std_logic;  
  SIGNAL IR_zd        : std_logic;     
  SIGNAL MBF1Neg_zd   : std_logic;    
  SIGNAL MBF2Neg_zd   : std_logic;   
  SIGNAL ORB_zd       : std_logic;  

  ------------------------------------------------------------------------------
  -- FIFO memory definitions
  ------------------------------------------------------------------------------
  -- general
  CONSTANT FIFOWordLength  :  positive := 36;
  SUBTYPE  FIFOWord    IS std_logic_vector(FIFOWordLength - 1 DOWNTO 0);
  TYPE     FIFOArray   IS ARRAY (0 TO FIFOSize - 1) OF FIFOWord;
  
  CONSTANT MailWordLength  :  positive := 36;
  SUBTYPE  MailWord    IS std_logic_vector(MailWordLength - 1 DOWNTO 0);
  
  CONSTANT Offs_Par_Number :  positive := 2; -- Number of Words while
  					     -- Parallel Offset Loading
  CONSTANT Offs_Ser_Number :  positive := OffsetSize*2; -- Number of Bits while
  					     -- Serial Offset Loading
  CONSTANT Offs_Val_Limit :  positive := FIFOSize-4; -- offset value limit while
  					     --  Offset Loading
  -- special
  CONSTANT FIFOWordBytes   :  positive := 4;
    
  ------------------------------------------------------------------------------
  -- internal signals 
  ------------------------------------------------------------------------------
  -- FIFO Arrays
  
     SIGNAL FIFOMemory1int : FIFOArray := (FIFOArray'range =>
                                        FIFOWord'(OTHERS => 'X'));

  -- Main Registers                                       
     -- Input Registers
      
     SIGNAL InputReg1int   : FIFOWord := (OTHERS => 'X');
     
     -- Output Registers
      
     SIGNAL OutputReg1int  : FIFOWord := (OTHERS => 'X');
     
     -- FIFO Pointers
     
     SIGNAL ReadPtr1int    : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL WritePtr1int   : Natural RANGE 0 TO FIFOSize-1;
     
     SIGNAL ReadPtr1int_add : std_logic;
                                 -- additional high bits to differ cases when
     SIGNAL WritePtr1int_add : std_logic; -- FIFO empty or full

     SIGNAL ShadowReadPtrint    : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL ShadowReadPtrint_add : std_logic; 
     
     SIGNAL ReadPtr1_sel_int    : Natural RANGE 0 TO FIFOSize-1;
                                                -- selected from
     SIGNAL ReadPtr1_sel_int_add : std_logic;   -- ReadPtr and ShadowReadPtr
     
     -- FIFO Offset for Almoust Empty/Full Flags
     
     SIGNAL X1int, Y1int   : NATURAL RANGE 0 TO Offs_Val_Limit;
     
     -- Mail Registers
     
     SIGNAL Mail1int, Mail2int     : MailWord := (OTHERS => 'X');
    
     -- Flags 
     
     SIGNAL  IRint, ORint, EFNegint: std_ulogic;    
     SIGNAL  AE1int, AF1int : std_ulogic;
      
     ---------- Input Registers Controlling Signals ------------      
     -- Flags "Input Register is loaded" - in this 
     -- model they will be loaded to FIFOMemory on CLK negedge ------??     
     SIGNAL InputReg1Readyint   : std_ulogic; 

     ---------- Output Registers Controlling Signals ------------      
    
     SIGNAL FWFTFirst : std_ulogic:='1'; -- first word though in FWFT mode
     
     -------------------------------------------------------------------------  
     --  Reset 
     
     SIGNAL RST1int: std_ulogic;
     SIGNAL MRSDoneint: std_ulogic := '0';
 
     -- Counters of Clocks during Master/Partion Reset is active or just after
     -- Reset
     
     SIGNAL CountCLKA1int, CountCLKB1int : Natural;
         
     -- Internal Control Signals
     
     SIGNAL EnWrFIFO1int, EnRdFIFO1int,
     	    EnWrMail1int, EnRdMail1int, EnWrMail2int, EnRdMail2int: std_ulogic; 
     	    
     ---------------------------------------------------------------------------
     -- ALmost-Empty/Almost-Full Offsets Loading Mode
     
     SIGNAL Offs_Par_Load_Modeint : std_ulogic := '0';
                                            -- Parallel Offsets Loading Mode
     SIGNAL Offs_Ser_Load_Modeint : std_ulogic := '0';
                                            -- Serial Offsets Loading Mode
     
     -- Word/Bit Counter while Offset Loading
     
     SIGNAL CountLoadOffsetint: Natural; 
     -------------------------------------------------------------------
     --Retransmit mode signals
      
     SIGNAL RetModeBegint, Ret1int, Ret2int: std_ulogic;
     ---------------------------------------------------------------------------
     -- Additional Signals
     
     SIGNAL SIZBint: std_ulogic;
     
    ----------------------------------------------------------------------------
    -- Internal Signals for Full /Empty  FLAGS implementation according
    -- to IDT Verilog gate-level model simulation 
    
    SIGNAL STATE1B,STATE2A:STD_LOGIC;
    SIGNAL F1ORB,F2ORB,F3ORB,WrORB,WrFORB,BYPB:STD_LOGIC;
    SIGNAL F1IRA,F2IRA,WrIRA,WrFIRA :STD_LOGIC;
    SIGNAL B0C1ORB: NATURAL;
    SIGNAL B0C1IRA: NATURAL;
    SIGNAL OPTEO :STD_LOGIC;
    SIGNAL En_ORB, En2_ORB : STD_LOGIC;
    SIGNAL Counter1_ORB, Counter2_ORB : STD_LOGIC;
    SIGNAL EFlGen_B, EF1l_B, EF2l_B, ORB_B2 : STD_LOGIC;
    SIGNAL EF2l_B_add : STD_LOGIC;
    SIGNAL AFTEn_AE_B, Eql_ORB, Eq_ORB : STD_LOGIC;
    SIGNAL BMAft_ORB, BMAft_Reg3 : STD_LOGIC;
    SIGNAL RDP_1, ReadPtr1_l_int    : Natural RANGE 0 TO FIFOSize-1;
    SIGNAL ReadPtr1_l_int_add : std_logic; 
    
    ----------------------------------------------------------------------------
    -- Internal Signals for AFA/AEA/AFB/AEB FLAGS implementation according
    -- to IDT Verilog gate-level model simulation 
    
    SIGNAL IRHdl2 : STD_LOGIC;
    SIGNAL UniEnl : STD_LOGIC := '1';
    SIGNAL BEFWFTl : STD_LOGIC;
    SIGNAL MRSTl1, PRSTl1 : STD_LOGIC;
    SIGNAL Rd_Ptr1, Wr_Ptr1 : STD_LOGIC_VECTOR (FIFOPOWER -1 DOWNTO 0);
    SIGNAL AFlGen_A, AF1l_A, AF2l_A, AFlA : STD_LOGIC; 
    SIGNAL RcvEn_AF_A, BCmpEn_AF_A : STD_LOGIC;
    SIGNAL AElGen_B, AE1l_B, AE2l_B, AElB : STD_LOGIC; 
    SIGNAL RcvEn_AE_B, BCmpEn_AE_B : STD_LOGIC;
    SIGNAL AF_A, AE_B : STD_LOGIC_VECTOR (FIFOPOWER - 1 DOWNTO 0);
  
  BEGIN -- VitalBehavior block
     
--------------------------------------------------------------------------------
-- Timing Check Section                                                         
--------------------------------------------------------------------------------

     TimingChecks: PROCESS ( A_ipd, B_ipd,   CLKA, CLKB, CSANeg, CSBNeg,
       ENA, ENB, FS0SD, FS1SEN, MBA, MBB,  RFM , RTM ,RSTNeg,
         WRA, WRB)

    -- Timing Check Variables

    -- Pulse Width Check Variables
      VARIABLE Pviol_CLKA          : X01 := '0';
      VARIABLE PD_CLKA             : VitalPeriodDataType := VitalPeriodDataInit;

      VARIABLE Pviol_CLKB          : X01 := '0';
      VARIABLE PD_CLKB             : VitalPeriodDataType := VitalPeriodDataInit;

    -- Setup/Hold Check Variables
      VARIABLE Tviol_A0_CLKA       : X01 := '0';
      VARIABLE TD_A0_CLKA          : VitalTimingDataType;

      VARIABLE TViol_B0_CLKB       : X01 := '0';
      VARIABLE TD_B0_CLKB          : VitalTimingDataType;

      VARIABLE Tviol_CSANeg_CLKA   : X01 := '0';
      VARIABLE TD_CSANeg_CLKA      : VitalTimingDataType;

      VARIABLE Tviol_WRA_CLKA      : X01 := '0';
      VARIABLE TD_WRA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_ENA_CLKA      : X01 := '0';
      VARIABLE TD_ENA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_MBA_CLKA      : X01 := '0';
      VARIABLE TD_MBA_CLKA         : VitalTimingDataType;

      VARIABLE Tviol_CSBNeg_CLKB   : X01 := '0';
      VARIABLE TD_CSBNeg_CLKB      : VitalTimingDataType;

      VARIABLE Tviol_WRB_CLKB      : X01 := '0';
      VARIABLE TD_WRB_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_ENB_CLKB      : X01 := '0';
      VARIABLE TD_ENB_CLKB         : VitalTimingDataType;

      VARIABLE Tviol_MBB_CLKB      : X01 := '0';
      VARIABLE TD_MBB_CLKB         : VitalTimingDataType;