idt72v241.vhd

VHDL的ram和fifo model code 包含众多的厂家

-------------------------------------------------------------------------------
--  File name : idt72V241.vhd
-------------------------------------------------------------------------------
--  Copyright (C) 1998 Integrated Device Technology; http://www.idt.com/
--  Developed by SEVA Technologies Inc. (Moscow branch) under contract to IDT
--  and supported by Free Model Foundry; http://www.FreeModelFoundry.com
--
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
--
--  This VHDL model is provided on an "AS IS" basis and IDT makes absolutely no
--  warranty with respect to the information contained herein. IDT DISCLAIMS
--  AND CUSTOMER WAIVES ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING
--  WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE
--  ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE USER ACCORDINGLY, IN
--  NO EVENT SHALL IDT BE LIABLE FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN
--  CONTRACT OR TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL,
--  CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR
--  APPLICATION OF THE VHDL model. Further, IDT reserves the right to make
--  changes without notice to any product herein to improve reliability,
--  function, or design.  IDT does not convey any license under patent rights
--  or any other intellectual property rights, including those of third parties.
--  IDT is not obligated to provide maintenance or support for the licensed VHDL
--  model.
--
-- MODIFICATION HISTORY :
--
-- version | author     | mod date  | changes made
--   V1.0  |  ZGA, PAV  | 98 MAY 17 | initial coding
--   V1.1  | R. Munden  | 02 MAY 19 | licensing changed to GPL
-------------------------------------------------------------------------------
-- PART DESCRIPTION :
--
-- Library:          IDT_FIFO
-- Technology:       CMOS
-- Part:             IDT72V241
--
-- Description: SyncFIFO Memory 4096x9
--
-------------------------------------------------------------------------------

LIBRARY ieee;    USE ieee.vital_primitives.ALL;
                 USE ieee.vital_timing.ALL;
                 USE ieee.std_logic_1164.ALL;

LIBRARY fmf;     USE fmf.ff_package.ALL;
                 USE fmf.gen_utils.ALL;
                 USE fmf.conversions.to_nat;
                 USE fmf.conversions.to_slv;

-------------------------------------------------------------------------------
-- ENTITY DECLARATION
-------------------------------------------------------------------------------

ENTITY IDT72V241 IS

        GENERIC (
                 -- tipd delays: interconnect path delays
                 --              (there must be one generic for each input pin)

                 tipd_D0        : VitalDelayType01  := VitalZeroDelay01;
                 tipd_D1        : VitalDelayType01  := VitalZeroDelay01;
                 tipd_D2        : VitalDelayType01  := VitalZeroDelay01;
                 tipd_D3        : VitalDelayType01  := VitalZeroDelay01;
                 tipd_D4        : VitalDelayType01  := VitalZeroDelay01;
                 tipd_D5        : VitalDelayType01  := VitalZeroDelay01;
                 tipd_D6        : VitalDelayType01  := VitalZeroDelay01;
                 tipd_D7        : VitalDelayType01  := VitalZeroDelay01;
                 tipd_D8        : VitalDelayType01  := VitalZeroDelay01;
                 tipd_RSNeg     : VitalDelayType01  := VitalZeroDelay01;
                 tipd_WCLK      : VitalDelayType01  := VitalZeroDelay01;
                 tipd_WEN1Neg   : VitalDelayType01  := VitalZeroDelay01;
                 tipd_WEN2LDNeg : VitalDelayType01  := VitalZeroDelay01;
                 tipd_RCLK      : VitalDelayType01  := VitalZeroDelay01;
                 tipd_REN1Neg   : VitalDelayType01  := VitalZeroDelay01;
                 tipd_REN2Neg   : VitalDelayType01  := VitalZeroDelay01;
                 tipd_OENeg     : VitalDelayType01  := VitalZeroDelay01;

                 -- tpd delays: propagation delays

                 -- tRSF ( for all flag )
                 tpd_RSNeg_EFNeg  : VitalDelayType01 := UnitDelay01;

                 -- tRSF (applicable for Q)
                 tpd_RSNeg_Q0   : VitalDelayType01Z := UnitDelay01Z;

                 -- tA   (applicable for RCLKxQ-valid
                 tpd_RCLK_Q0      : VitalDelayType01Z := UnitDelay01Z;

                 -- tOLZ/tOE/tOHZ
                 tpd_OENeg_Q0   : VitalDelayType01Z := UnitDelay01Z;

                 -- tWFF
                 tpd_WCLK_FFNeg : VitalDelayType01 := UnitDelay01;

                 -- tREF
                 tpd_RCLK_EFNeg : VitalDelayType01 := UnitDelay01;

                 -- tPAF
                 tpd_WCLK_PAFNeg : VitalDelayType01 := UnitDelay01;

                 -- tPAE
                 tpd_RCLK_PAENeg : VitalDelayType01 := UnitDelay01;

                 -- tpw values: pulse widths

                 -- tRCLKH
                 tpw_RCLK_posedge : VitalDelayType := UnitDelay;
                 -- tRCLKL
                 tpw_RCLK_negedge : VitalDelayType := UnitDelay;
                 -- tRS
                 tpw_RSNeg_negedge : VitalDelayType := UnitDelay;

                 -- tperiod values: min calculated as 1/max freq

                 -- tperiod_RCLK_posedge
                 tperiod_RCLK_posedge : VitalDelayType := UnitDelay;
                 -- tWCLK
                 tperiod_WCLK_posedge : VitalDelayType := UnitDelay;

                 -- tsetup values: setup times

                 -- tDS
                 tsetup_D0_WCLK        : VitalDelayType := UnitDelay;
                 -- tENS
                 tsetup_REN1Neg_RCLK   : VitalDelayType := UnitDelay;

                 -- tRSS
                 tsetup_REN1Neg_RSNeg   : VitalDelayType := UnitDelay;

                 -- thold values: hold times

                 -- tDH
                 thold_D0_WCLK        : VitalDelayType := UnitDelay;
                 -- tENH
                 thold_REN1Neg_RCLK   : VitalDelayType := UnitDelay;

                 -- trecovery values: recovery times

                 -- tRSR (applicable for both REN and WEN)
                 trecovery_REN1Neg_RSNeg  : VitalDelayType := UnitDelay;

                 -- tskew values(Note: these values are passed through the
                 --                    SDF DEVICE construct)

                 -- tSKEW1 (skew time /RCLK/WCLK(for FFIR)
                 tdevice_SKEW1 : VitalDelayType := UnitDelay;
                 -- tSKEW2 (skew time /RCLK/WCLK(for PAE&PAF)
                 tdevice_SKEW2  : VitalDelayType := UnitDelay;

                 -- generic control parameters

                 InstancePath    : STRING  := DefaultInstancePath;
                 TimingChecksOn  : BOOLEAN := DefaultTimingChecks;
                 MsgOn           : BOOLEAN := DefaultMsgOn;
                 XOn             : BOOLEAN := DefaultXOn;
                 TimingModel     : STRING  := DefaultTimingModel
            );

      PORT (
           D0        : IN  std_logic := 'X';  --------------------------------
           D1        : IN  std_logic := 'X';  --
           D2        : IN  std_logic := 'X';  --
           D3        : IN  std_logic := 'X';  --
           D4        : IN  std_logic := 'X';  --  Data Input Bus
           D5        : IN  std_logic := 'X';  --
           D6        : IN  std_logic := 'X';  --
           D7        : IN  std_logic := 'X';  --
           D8        : IN  std_logic := 'X';  --------------------------------
           RSNeg     : IN  std_logic := 'X';  --  Reset
           WCLK      : IN  std_logic := 'X';  --  Write Clock
           WEN1Neg   : IN  std_logic := 'X';  --  Write Enable 1
           WEN2LDNeg : IN  std_logic := 'X';  --  Write Enable 2
           RCLK      : IN  std_logic := 'X';  --  Read Clock
           REN1Neg   : IN  std_logic := 'X';  --  Read Enabled 1
           REN2Neg   : IN  std_logic := 'X';  --  Read Enabled 2
           OENeg     : IN  std_logic := 'X';  --  Output Enable
           Q0        : OUT std_logic := 'U';  --------------------------------
           Q1        : OUT std_logic := 'U';  --
           Q2        : OUT std_logic := 'U';  --
           Q3        : OUT std_logic := 'U';  --
           Q4        : OUT std_logic := 'U';  --  Data Output Bus
           Q5        : OUT std_logic := 'U';  --
           Q6        : OUT std_logic := 'U';  --
           Q7        : OUT std_logic := 'U';  --
           Q8        : OUT std_logic := 'U';  --------------------------------
           EFNeg     : OUT std_logic := 'U';  --  Empty Flag
           PAENeg    : OUT std_logic := 'U';  --  Programmable Almost-Empty Flag
           PAFNeg    : OUT std_logic := 'U';  --  Programmable Almost-Full Flag
           FFNeg     : OUT std_logic := 'U'   --  Full Flag
      );

           ATTRIBUTE vital_level0 OF IDT72V241: ENTITY IS True;

      END IDT72V241;

-----------------------------------------------------------------------
--  ARCHITECTURE DECLARATION
-----------------------------------------------------------------------

ARCHITECTURE vhdl_behavioral OF IDT72V241 IS

    ATTRIBUTE vital_level0 OF vhdl_behavioral : ARCHITECTURE IS True;

    CONSTANT partID : String := "IDT72V241";

  -- delayed inputs (func. sec. must use these signals instead of actual inputs)
    SIGNAL D0_ipd        : std_ulogic := 'X';
    SIGNAL D1_ipd        : std_ulogic := 'X';
    SIGNAL D2_ipd        : std_ulogic := 'X';
    SIGNAL D3_ipd        : std_ulogic := 'X';
    SIGNAL D4_ipd        : std_ulogic := 'X';
    SIGNAL D5_ipd        : std_ulogic := 'X';
    SIGNAL D6_ipd        : std_ulogic := 'X';
    SIGNAL D7_ipd        : std_ulogic := 'X';
    SIGNAL D8_ipd        : std_ulogic := 'X';
    SIGNAL RSNeg_ipd     : std_ulogic := 'X';
    SIGNAL WCLK_ipd      : std_ulogic := 'X';
    SIGNAL WEN1Neg_ipd   : std_ulogic := 'X';
    SIGNAL WEN2LDNeg_ipd : std_ulogic := 'X';
    SIGNAL RCLK_ipd      : std_ulogic := 'X';
    SIGNAL REN1Neg_ipd   : std_ulogic := 'X';
    SIGNAL REN2Neg_ipd   : std_ulogic := 'X';
    SIGNAL OENeg_ipd     : std_ulogic := 'X';

    -- FIFO memory definations
    CONSTANT FIFOSize       : positive := 4096;
    CONSTANT FIFOWordLenght : positive := 9;
    SUBTYPE  FIFOWord       is std_logic_vector(0 to FIFOWordLenght - 1);
    TYPE     FIFOArray      is array (0 to FIFOSize) of FIFOWord;
    TYPE     FIFOStates     is (unknown, standby, idle);

    -- internal signals

    SIGNAL Pointer     : Natural RANGE 0 TO FIFOSize := FIFOSize-1;
    SIGNAL EmptyOffReg : Natural;
    SIGNAL FullOffReg  : Natural;
    SIGNAL OffRegSwitch: Natural;
    SIGNAL Start : std_ulogic := '0';

    -- SKEW stuff (see also generics list)

    ALIAS  tSKEW1          : VitalDelayType IS tdevice_SKEW1;
    ALIAS  tSKEW2          : VitalDelayType IS tdevice_SKEW2;
    SIGNAL tSKEW_WCLK_RCLK : Time := 0 ns;    -- actual /WCLK/RCLK skew time
    SIGNAL tSKEW_RCLK_WCLK : Time := 0 ns;    -- actual /RCLK/WCLK skew time
    SIGNAL OpenIn, OpenOut : std_logic;
    ALIAS  tRCLK           : VitalDelayType IS tperiod_RCLK_posedge;
    ALIAS  tWCLK           : VitalDelayType IS tperiod_WCLK_posedge;


BEGIN
--------------------------------------------------------------------------------
-- Dummy instances for exporting tSKEW vals from SDF file
-- using DEVICE construct
--------------------------------------------------------------------------------

  SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1));

  SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2));

    -------------------------------------------------------------------
    -- Wire Delays
    -------------------------------------------------------------------
    WireDelay: BLOCK
    BEGIN

      w_1:  VitalWireDelay (D0_ipd       , D0       , tipd_D0        );
      w_2:  VitalWireDelay (D1_ipd       , D1       , tipd_D1        );
      w_3:  VitalWireDelay (D2_ipd       , D2       , tipd_D2        );
      w_4:  VitalWireDelay (D3_ipd       , D3       , tipd_D3        );
      w_5:  VitalWireDelay (D4_ipd       , D4       , tipd_D4        );
      w_6:  VitalWireDelay (D5_ipd       , D5       , tipd_D5        );
      w_7:  VitalWireDelay (D6_ipd       , D6       , tipd_D6        );
      w_8:  VitalWireDelay (D7_ipd       , D7       , tipd_D7        );
      w_9:  VitalWireDelay (D8_ipd       , D8       , tipd_D8        );
      w_11: VitalWireDelay (RSNeg_ipd    , RSNeg    , tipd_RSNeg     );
      w_12: VitalWireDelay (WCLK_ipd     , WCLK     , tipd_WCLK      );
      w_13: VitalWireDelay (WEN1Neg_ipd  , WEN1Neg  , tipd_WEN1Neg   );
      w_14: VitalWireDelay (WEN2LDNeg_ipd, WEN2LDNeg, tipd_WEN2LDNeg );