📄 sy69167.vhd
字号:
HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D11_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D11_CLK ); VitalSetupHoldCheck ( TestSignal => D12_ipd, TestSignalName => "D12_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D12_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D12_CLK ); VitalSetupHoldCheck ( TestSignal => D13_ipd, TestSignalName => "D13_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D13_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D13_CLK ); VitalSetupHoldCheck ( TestSignal => D14_ipd, TestSignalName => "D14_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D14_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D14_CLK ); VitalSetupHoldCheck ( TestSignal => D15_ipd, TestSignalName => "D15_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D15_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D15_CLK ); VitalSetupHoldCheck ( TestSignal => D16_ipd, TestSignalName => "D16_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D16_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D16_CLK ); VitalSetupHoldCheck ( TestSignal => D17_ipd, TestSignalName => "D17_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_D17_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_D17_CLK ); VitalSetupHoldCheck ( TestSignal => WRNeg_ipd, TestSignalName => "WRNeg_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_WRNeg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_WRNeg_CLK ); VitalSetupHoldCheck ( TestSignal => RDNeg_ipd, TestSignalName => "RDNeg_ipd", RefSignal => CLK_ipd, RefSignalName => "CLK_ipd", SetupHigh => tsetup_D0_CLK, SetupLow => tsetup_D0_CLK, HoldHigh => thold_D0_CLK, HoldLow => thold_D0_CLK, CheckEnabled => TRUE, RefTransition => '/', HeaderMsg => InstancePath & "/sy69167", TimingData => TD_RDNeg_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Tviol_RDNeg_CLK ); VitalPeriodPulseCheck ( TestSignal => CLK_ipd, TestSignalName => "CLK_ipd", Period => tperiod_CLK_posedge, PulseWidthHigh => tpw_CLK_posedge, PulseWidthLow => tpw_CLK_negedge, PeriodData => PD_CLK, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_CLK, HeaderMsg => InstancePath & "/sy69167", CheckEnabled => TRUE ); VitalPeriodPulseCheck ( TestSignal => WRNeg_ipd, TestSignalName => "WRNeg_ipd", PulseWidthLow => tpw_WRNeg_negedge, PeriodData => PD_WRNeg, XOn => XOn, MsgOn => MsgOn, Violation => Pviol_WRNeg, HeaderMsg => InstancePath & "/sy69167", CheckEnabled => TRUE ); END IF; -- Timing Check Section ------------------------------------------------------------------------ -- Functionality Section ------------------------------------------------------------------------ Violation := Pviol_CLK OR Pviol_WRNeg OR Tviol_WRNeg_CLK OR Tviol_D0_CLK OR Tviol_D1_CLK OR Tviol_D2_CLK OR Tviol_D3_CLK OR Tviol_D4_CLK OR Tviol_D5_CLK OR Tviol_D6_CLK OR Tviol_D7_CLK OR Tviol_D8_CLK OR Tviol_D9_CLK OR Tviol_D10_CLK OR Tviol_D11_CLK OR Tviol_D12_CLK OR Tviol_D13_CLK OR Tviol_D14_CLK OR Tviol_D15_CLK OR Tviol_D16_CLK OR Tviol_D17_CLK OR Tviol_RDNeg_CLK; IF (Violation = 'X') THEN DataDrive := (OTHERS => 'X'); FULL_zd := 'X'; HALF_zd := 'X'; EMPTY_zd := 'X'; OVFLOW_zd := 'X'; UNFLOW_zd := 'X'; ELSIF (RSTNeg_nwv = '0') THEN RDPoint := 0; WRPoint := 0; Count := 0; FULL_zd := '0'; HALF_zd := '0'; EMPTY_zd := '1'; OVFLOW_zd := '0'; UNFLOW_zd := '0'; ELSIF (CLKint = '1' and CLKint'EVENT) THEN IF (WRNeg_nwv = '0') THEN IF (FULL_zd = '1' AND INHIBIT_nwv = '1') THEN NULL; ELSE DataGet(17) := D17_ipd; DataGet(16) := D16_ipd; DataGet(15) := D15_ipd; DataGet(14) := D14_ipd; DataGet(13) := D13_ipd; DataGet(12) := D12_ipd; DataGet(11) := D11_ipd; DataGet(10) := D10_ipd; DataGet(9) := D9_ipd; DataGet(8) := D8_ipd; DataGet(7) := D7_ipd; DataGet(6) := D6_ipd; DataGet(5) := D5_ipd; DataGet(4) := D4_ipd; DataGet(3) := D3_ipd; DataGet(2) := D2_ipd; DataGet(1) := D1_ipd; DataGet(0) := D0_ipd; -- Check for unusable data bits FOR i IN 0 TO 17 LOOP IF ((DataGet(i) = '1' NOR DataGet(i) = '0') NOR (DataGet(i) = 'L' NOR DataGet(i) = 'H')) THEN ASSERT FALSE REPORT "DATA BUS ERRROR! ZEROS LOADED INTO MEMORY!" SEVERITY WARNING; END IF; END LOOP; DataIn := To_bitvector(DataGet); MemData(WRPoint) := DataIn; EMPTY_zd := '0'; IF (FULL_zd = '1') THEN OVFLOW_zd := '1'; ELSE OVFLOW_zd := '0'; END IF; IF (Count >= 32) THEN HALF_zd := '1'; ELSE HALF_zd := '0'; END IF; IF (Count = 63) THEN FULL_zd := '1'; ELSE FULL_zd := '0'; Count := Count + 1; END IF; IF (WRPoint = 63) THEN WRPoint := 0; ELSE WRPoint := WRPoint + 1; END IF; END IF; ELSIF (RDNeg_nwv = '0') THEN IF (EMPTY_zd = '1' AND INHIBIT_nwv = '1') THEN NULL; ELSE DataOut := MemData(RDPoint); DataDrive := To_StdLogicVector(DataOut); FULL_zd := '0'; IF (EMPTY_zd = '1') THEN UNFLOW_zd := '1'; ELSE UNFLOW_zd := '0'; END IF; IF (Count >= 32) THEN HALF_zd := '1'; ELSE HALF_zd := '0'; END IF; IF (Count = 0) THEN EMPTY_zd := '1'; ELSE EMPTY_zd := '0'; Count := Count - 1; END IF; IF (RDPoint = 63) THEN RDPoint := 0; ELSE RDPoint := RDPoint + 1; END IF; END IF; END IF; END IF; ------------------------------------------------------------------------ -- Path Delay Section ------------------------------------------------------------------------ VitalPathDelay01 ( OutSignal => Q0int, OutSignalName => "Q0", OutTemp => Q0_zd, GlitchData => Q0_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT, PathDelay => tpd_CLK_Q0, PathCondition => TRUE) ) ); VitalPathDelay01 ( OutSignal => Q1int, OutSignalName => "Q1", OutTemp => Q1_zd, GlitchData => Q1_GlitchData, XOn => XOn, MsgOn => MsgOn, Paths => ( 0 => (InputChangeTime => CLKint'LAST_EVENT,⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -