sy69167.vhd

VHDL的ram和fifo model code 包含众多的厂家

--------------------------------------------------------------------------------
--  File Name: sy69167.vhd
--------------------------------------------------------------------------------
--  Copyright (C) 1998 Free Model Foundry; http://www.FreeModelFoundry.com
-- 
--  This program is free software; you can redistribute it and/or modify
--  it under the terms of the GNU General Public License version 2 as
--  published by the Free Software Foundation.
-- 
--  MODIFICATION HISTORY:
-- 
--  version: |  author:  | mod date: | changes made:
--    V1.0     R. Steele   98 JAN 12   Conformed to style guide
-- 
--------------------------------------------------------------------------------
--  PART DESCRIPTION:
-- 
--  Library:     FIFO
--  Technology:  ECL
--  Part:        SY69167
-- 
--  Description: 64 X 18 FIFO
--------------------------------------------------------------------------------

LIBRARY IEEE;   USE IEEE.std_logic_1164.ALL;
                USE IEEE.VITAL_timing.ALL;
                USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF;    USE FMF.gen_utils.ALL;
                USE FMF.ecl_utils.ALL;
--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY sy69167 IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_CLKNeg         : VitalDelayType01 := VitalZeroDelay01;
        tipd_CLK            : VitalDelayType01 := VitalZeroDelay01;
        tipd_RDNeg          : VitalDelayType01 := VitalZeroDelay01;
        tipd_WRNeg          : VitalDelayType01 := VitalZeroDelay01;
        tipd_RSTNeg         : VitalDelayType01 := VitalZeroDelay01;
        tipd_INHIBIT        : VitalDelayType01 := VitalZeroDelay01;
        tipd_D0             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D1             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D2             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D3             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D4             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D5             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D6             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D7             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D8             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D9             : VitalDelayType01 := VitalZeroDelay01;
        tipd_D10            : VitalDelayType01 := VitalZeroDelay01;
        tipd_D11            : VitalDelayType01 := VitalZeroDelay01;
        tipd_D12            : VitalDelayType01 := VitalZeroDelay01;
        tipd_D13            : VitalDelayType01 := VitalZeroDelay01;
        tipd_D14            : VitalDelayType01 := VitalZeroDelay01;
        tipd_D15            : VitalDelayType01 := VitalZeroDelay01;
        tipd_D16            : VitalDelayType01 := VitalZeroDelay01;
        tipd_D17            : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        tpd_CLK_Q0                      : VitalDelayType01  := UnitDelay01;
        tpd_CLK_FULL                    : VitalDelayType01  := UnitDelay01;
        tpd_CLK_HALF                    : VitalDelayType01  := UnitDelay01;
        tpd_CLK_EMPTY                   : VitalDelayType01  := UnitDelay01;
        tpd_CLK_OVFLOW                  : VitalDelayType01  := UnitDelay01;
        tpd_CLK_UNFLOW                  : VitalDelayType01  := UnitDelay01;
        tpd_RSTNeg_FULL                 : VitalDelayType01  := UnitDelay01;
        tpd_RSTNeg_HALF                 : VitalDelayType01  := UnitDelay01;
        tpd_RSTNeg_EMPTY                : VitalDelayType01  := UnitDelay01;
        tpd_RSTNeg_OVFLOW               : VitalDelayType01  := UnitDelay01;
        tpd_RSTNeg_UNFLOW               : VitalDelayType01  := UnitDelay01;
        -- tpw values: pulse widths
        tpw_WRNeg_negedge               : VitalDelayType    := UnitDelay;
        tpw_CLK_posedge                 : VitalDelayType    := UnitDelay;
        tpw_CLK_negedge                 : VitalDelayType    := UnitDelay;
        -- tperiod_min: minimum clock period = 1/max freq
        tperiod_CLK_posedge             : VitalDelayType    := UnitDelay;
        -- tsetup values: setup times
        tsetup_D0_CLK                   : VitalDelayType    := UnitDelay;
        -- thold values: hold times
        thold_D0_CLK                    : VitalDelayType    := UnitDelay;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXOn;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        CLK             : IN    std_logic := 'X';
        CLKNeg          : IN    std_logic := 'X';
        RDNeg           : IN    std_logic := 'X';
        WRNeg           : IN    std_logic := 'X';
        RSTNeg          : IN    std_logic := 'X';
        INHIBIT         : IN    std_logic := 'X';

        D0              : IN    std_logic := 'X';
        D1              : IN    std_logic := 'X';
        D2              : IN    std_logic := 'X';
        D3              : IN    std_logic := 'X';
        D4              : IN    std_logic := 'X';
        D5              : IN    std_logic := 'X';
        D6              : IN    std_logic := 'X';
        D7              : IN    std_logic := 'X';
        D8              : IN    std_logic := 'X';
        D9              : IN    std_logic := 'X';
        D10             : IN    std_logic := 'X';
        D11             : IN    std_logic := 'X';
        D12             : IN    std_logic := 'X';
        D13             : IN    std_logic := 'X';
        D14             : IN    std_logic := 'X';
        D15             : IN    std_logic := 'X';
        D16             : IN    std_logic := 'X';
        D17             : IN    std_logic := 'X';

        FULL            : OUT   std_logic := 'U';
        HALF            : OUT   std_logic := 'U';
        EMPTY           : OUT   std_logic := 'U';
        OVFLOW          : OUT   std_logic := 'U';
        UNFLOW          : OUT   std_logic := 'U';

        Q0              : OUT   std_logic := 'U';
        Q1              : OUT   std_logic := 'U';
        Q2              : OUT   std_logic := 'U';
        Q3              : OUT   std_logic := 'U';
        Q4              : OUT   std_logic := 'U';
        Q5              : OUT   std_logic := 'U';
        Q6              : OUT   std_logic := 'U';
        Q7              : OUT   std_logic := 'U';
        Q8              : OUT   std_logic := 'U';
        Q9              : OUT   std_logic := 'U';
        Q10             : OUT   std_logic := 'U';
        Q11             : OUT   std_logic := 'U';
        Q12             : OUT   std_logic := 'U';
        Q13             : OUT   std_logic := 'U';
        Q14             : OUT   std_logic := 'U';
        Q15             : OUT   std_logic := 'U';
        Q16             : OUT   std_logic := 'U';
        Q17             : OUT   std_logic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of sy69167 : ENTITY IS TRUE;
END sy69167;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of sy69167 IS
    ATTRIBUTE VITAL_LEVEL1 of vhdl_behavioral : ARCHITECTURE IS FALSE;

    SIGNAL D0_ipd           : std_ulogic := 'X';
    SIGNAL D1_ipd           : std_ulogic := 'X';
    SIGNAL D2_ipd           : std_ulogic := 'X';
    SIGNAL D3_ipd           : std_ulogic := 'X';
    SIGNAL D4_ipd           : std_ulogic := 'X';
    SIGNAL D5_ipd           : std_ulogic := 'X';
    SIGNAL D6_ipd           : std_ulogic := 'X';
    SIGNAL D7_ipd           : std_ulogic := 'X';
    SIGNAL D8_ipd           : std_ulogic := 'X';
    SIGNAL D9_ipd           : std_ulogic := 'X';
    SIGNAL D10_ipd          : std_ulogic := 'X';
    SIGNAL D11_ipd          : std_ulogic := 'X';
    SIGNAL D12_ipd          : std_ulogic := 'X';
    SIGNAL D13_ipd          : std_ulogic := 'X';
    SIGNAL D14_ipd          : std_ulogic := 'X';
    SIGNAL D15_ipd          : std_ulogic := 'X';
    SIGNAL D16_ipd          : std_ulogic := 'X';
    SIGNAL D17_ipd          : std_ulogic := 'X';

    SIGNAL Q0int            : std_ulogic := 'X';
    SIGNAL Q1int            : std_ulogic := 'X';
    SIGNAL Q2int            : std_ulogic := 'X';
    SIGNAL Q3int            : std_ulogic := 'X';
    SIGNAL Q4int            : std_ulogic := 'X';
    SIGNAL Q5int            : std_ulogic := 'X';
    SIGNAL Q6int            : std_ulogic := 'X';
    SIGNAL Q7int            : std_ulogic := 'X';
    SIGNAL Q8int            : std_ulogic := 'X';
    SIGNAL Q9int            : std_ulogic := 'X';
    SIGNAL Q10int           : std_ulogic := 'X';
    SIGNAL Q11int           : std_ulogic := 'X';
    SIGNAL Q12int           : std_ulogic := 'X';
    SIGNAL Q13int           : std_ulogic := 'X';
    SIGNAL Q14int           : std_ulogic := 'X';
    SIGNAL Q15int           : std_ulogic := 'X';
    SIGNAL Q16int           : std_ulogic := 'X';
    SIGNAL Q17int           : std_ulogic := 'X';

    SIGNAL CLKint           : std_ulogic := 'X';
    SIGNAL FULLint          : std_ulogic := 'X';
    SIGNAL HALFint          : std_ulogic := 'X';
    SIGNAL EMPTYint         : std_ulogic := 'X';
    SIGNAL OVFLOWint        : std_ulogic := 'X';
    SIGNAL UNFLOWint        : std_ulogic := 'X';
    SIGNAL CLK_ipd          : std_ulogic := 'X';
    SIGNAL CLKNeg_ipd       : std_ulogic := 'X';
    SIGNAL RDNeg_ipd        : std_ulogic := 'X';
    SIGNAL WRNeg_ipd        : std_ulogic := 'X';
    SIGNAL RSTNeg_ipd       : std_ulogic := 'X';
    SIGNAL INHIBIT_ipd      : std_ulogic := 'X';


BEGIN
    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1: VitalWireDelay (CLK_ipd, CLK, tipd_CLK); 
        w_2: VitalWireDelay (CLKNeg_ipd, CLKNeg, tipd_CLKNeg);
        w_3: VitalWireDelay (RDNeg_ipd, RDNeg, tipd_RDNeg);
        w_4: VitalWireDelay (WRNeg_ipd, WRNeg, tipd_WRNeg);
        w_5: VitalWireDelay (RSTNeg_ipd, RSTNeg, tipd_RSTNeg);
        w_6: VitalWireDelay (INHIBIT_ipd, INHIBIT, tipd_INHIBIT);
        w_7: VitalWireDelay (D0_ipd, D0, tipd_D0);
        w_8: VitalWireDelay (D1_ipd, D1, tipd_D1);
        w_9: VitalWireDelay (D2_ipd, D2, tipd_D2);
        w_10: VitalWireDelay (D3_ipd, D3, tipd_D3);
        w_11: VitalWireDelay (D4_ipd, D4, tipd_D4);
        w_12: VitalWireDelay (D5_ipd, D5, tipd_D5);
        w_13: VitalWireDelay (D6_ipd, D6, tipd_D6);
        w_14: VitalWireDelay (D7_ipd, D7, tipd_D7);
        w_15: VitalWireDelay (D8_ipd, D8, tipd_D8);
        w_16: VitalWireDelay (D9_ipd, D9, tipd_D9);
        w_17: VitalWireDelay (D10_ipd, D10, tipd_D10);
        w_18: VitalWireDelay (D11_ipd, D11, tipd_D11);
        w_19: VitalWireDelay (D12_ipd, D12, tipd_D12);
        w_20: VitalWireDelay (D13_ipd, D13, tipd_D13);
        w_21: VitalWireDelay (D14_ipd, D14, tipd_D14);
        w_22: VitalWireDelay (D15_ipd, D15, tipd_D15);
        w_23: VitalWireDelay (D16_ipd, D16, tipd_D16);
        w_24: VitalWireDelay (D17_ipd, D17, tipd_D17);

    END BLOCK;

    ----------------------------------------------------------------------------
    -- Concurrent procedures
    ----------------------------------------------------------------------------
    a_1: VitalBUF(q => Q0, a => Q0int, Resultmap => ECL_wired_or_rmap);
    a_2: VitalBUF(q => Q1, a => Q1int, Resultmap => ECL_wired_or_rmap);
    a_3: VitalBUF(q => Q2, a => Q2int, Resultmap => ECL_wired_or_rmap);
    a_4: VitalBUF(q => Q3, a => Q3int, Resultmap => ECL_wired_or_rmap);
    a_5: VitalBUF(q => Q4, a => Q4int, Resultmap => ECL_wired_or_rmap);
    a_6: VitalBUF(q => Q5, a => Q5int, Resultmap => ECL_wired_or_rmap);
    a_7: VitalBUF(q => Q6, a => Q6int, Resultmap => ECL_wired_or_rmap);
    a_8: VitalBUF(q => Q7, a => Q7int, Resultmap => ECL_wired_or_rmap);
    a_9: VitalBUF(q => Q8, a => Q8int, Resultmap => ECL_wired_or_rmap);
    a_10: VitalBUF(q => Q9, a => Q9int, Resultmap => ECL_wired_or_rmap);
    a_11: VitalBUF(q => Q10, a => Q10int, Resultmap => ECL_wired_or_rmap);
    a_12: VitalBUF(q => Q11, a => Q11int, Resultmap => ECL_wired_or_rmap);
    a_13: VitalBUF(q => Q12, a => Q12int, Resultmap => ECL_wired_or_rmap);
    a_14: VitalBUF(q => Q13, a => Q13int, Resultmap => ECL_wired_or_rmap);
    a_15: VitalBUF(q => Q14, a => Q14int, Resultmap => ECL_wired_or_rmap);
    a_16: VitalBUF(q => Q15, a => Q15int, Resultmap => ECL_wired_or_rmap);
    a_17: VitalBUF(q => Q16, a => Q16int, Resultmap => ECL_wired_or_rmap);
    a_18: VitalBUF(q => Q17, a => Q17int, Resultmap => ECL_wired_or_rmap);
    a_19: VitalBUF(q => FULL, a => FULLint, Resultmap => ECL_wired_or_rmap);
    a_20: VitalBUF(q => HALF, a => HALFint, Resultmap => ECL_wired_or_rmap);
    a_21: VitalBUF(q => EMPTY, a => EMPTYint, Resultmap => ECL_wired_or_rmap);
    a_22: VitalBUF(q => OVFLOW, a => OVFLOWint, Resultmap => ECL_wired_or_rmap);
    a_23: VitalBUF(q => UNFLOW, a => UNFLOWint, Resultmap => ECL_wired_or_rmap);

    ----------------------------------------------------------------------------
    -- ECL Clock Process
    ----------------------------------------------------------------------------
    ECLClock : PROCESS (CLK_ipd, CLKNeg_ipd)

        -- Functionality Results Variables
        VARIABLE Mode           : X01;
        VARIABLE CLKint_zd      : std_ulogic;
        VARIABLE PrevData       : std_logic_vector(0 to 2);
 
        -- Output Glitch Detection Variables
 
    BEGIN
 
        ------------------------------------------------------------------------
        -- Functionality Section
        ------------------------------------------------------------------------
        Mode := ECL_diff_mode_tab (CLK_ipd, CLKNeg_ipd);

        VitalStateTable (
            StateTable      => ECL_clk_tab,
            DataIn          => (CLK_ipd, CLKNeg_ipd, Mode),
            Result          => CLKint_zd,
            PreviousDataIn  => PrevData
        );

        CLKint <= CLKint_zd;

    END PROCESS;

    ----------------------------------------------------------------------------
    -- Behavior Process
    ----------------------------------------------------------------------------
    VitalBehavior : PROCESS (CLKint, RSTNeg_ipd)
                         
        TYPE MemStore  IS ARRAY (0 to 63) OF BIT_VECTOR(17 DOWNTO 0);

        -- Functionality Results Variables
        VARIABLE FULL_zd        : std_ulogic;
        VARIABLE HALF_zd        : std_ulogic;
        VARIABLE EMPTY_zd       : std_ulogic;
        VARIABLE OVFLOW_zd      : std_ulogic;
        VARIABLE UNFLOW_zd      : std_ulogic;

        VARIABLE DataGet    : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'X');
        VARIABLE DataDrive  : std_logic_vector(17 DOWNTO 0) := (OTHERS => 'X');
        VARIABLE DataIn     : BIT_VECTOR(17 DOWNTO 0) := (OTHERS => '0');
        VARIABLE DataOut    : BIT_VECTOR(17 DOWNTO 0) := (OTHERS => '0');
        VARIABLE RDPoint    : INTEGER RANGE 0 TO 63 := 0;
        VARIABLE WRPoint    : INTEGER RANGE 0 TO 63 := 0;
        VARIABLE Count      : INTEGER RANGE 0 TO 63 := 0;
        VARIABLE MemData    : MemStore;

        ALIAS Q0_zd             : std_logic IS DataDrive(0);
        ALIAS Q1_zd             : std_logic IS DataDrive(1);
        ALIAS Q2_zd             : std_logic IS DataDrive(2);
        ALIAS Q3_zd             : std_logic IS DataDrive(3);
        ALIAS Q4_zd             : std_logic IS DataDrive(4);
        ALIAS Q5_zd             : std_logic IS DataDrive(5);