📄 idt72t4098.ftm

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<!DOCTYPE FTML SYSTEM "ftml.dtd"><FTML><HEAD><TITLE>FMF Timing for idt72t4098 Parts</TITLE><BODY><REVISION.HISTORY>version: |  author:     | mod date: | changes made:  V1.0     D.Vukicevic    05 Sep 06   Initial release</REVISION.HISTORY><TIMESCALE>1ns</TIMESCALE><MODEL>idt72t4098<FMFTIME>IDT72t4098L4BB<SOURCE>Integrated Device Technology DSC-5995/9, September 2004</SOURCE><COMMENT>The Values listed are for VCC=2.375V to 2.625V, CL=10pF, Ta=0 to 70CFor each parameter only minimum or maximum values were provided by the vendor, other values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH RCLK Q0 (0.6:1.9:3.2) (0.6:1.9:3.2) (1:2.1:3.2) (1:2.1:3.2) (1:2.1:3.2) (1:2.1:3.2))    (IOPATH OENeg Q0 (1:2.1:3.2) (1:2.1:3.2) (1:2.1:3.2) (0) (1:2.1:3.2) (0))    (IOPATH MRSNeg EFNeg (3.3:6.6:10) (3.3:6.6:10))    (IOPATH WCLK FFNeg (1:2.1:3.2) (1:2.1:3.2))    (IOPATH RCLK EFNeg (1:2.1:3.2) (1:2.1:3.2))    (IOPATH WCLK PAFNeg (1:2.1:3.2) (1:2.1:3.2))    (IOPATH RCLK PAENeg (1:2.1:3.2) (1:2.1:3.2))    (IOPATH RCLK ERCLK (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH RCLK ERENNeg (1:2.1:3.2) (1:2.1:3.2))  ))  (TIMINGCHECK    (SETUP D0 WCLK (1.2:1.2:1.2))    (SETUP RENNeg RCLK (1.2:1.2:1.2))    (SETUP WCSNeg WCLK (1.2:1.2:1.2))    (SETUP SI SCLK (15:15:15))    (SETUP SENNeg SCLK (5:5:5))    (SETUP RENNeg MRSNeg (15:15:15))    (SETUP HSTL MRSNeg (4:4:4))    (HOLD D0 WCLK (0.5:0.5:0.5))    (HOLD RENNeg RCLK (.5:.5:.5))    (HOLD WCSNeg WCLK (.5:.5:.5))    (HOLD SI SCLK (5:5:5))    (HOLD SENNeg SCLK (5:5:5))    (RECOVERY RENNeg MRSNeg (10:10:10))    (WIDTH (negedge MRSNeg) (30:30:30))    (WIDTH (COND SDR (negedge RCLK)) (1.8:1.8:1.8))    (WIDTH (COND SDR (posedge RCLK)) (1.8:1.8:1.8))    (WIDTH (COND DDR (negedge RCLK)) (4:4:4))    (WIDTH (COND DDR (posedge RCLK)) (4:4:4))    (WIDTH (negedge SCLK) (45:45:45))    (WIDTH (posedge SCLK) (45:45:45))    (PERIOD (COND SDR (posedge RCLK)) (4:4:4))    (PERIOD (COND DDR (posedge RCLK)) (9.1:9.1:9.1))    (PERIOD (posedge SCLK) (100:100:100))  ))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE (DEVICE(3.5:3.5:3.5)))))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE (DEVICE(3.5:3.5:3.5)))))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW3) (DELAY (ABSOLUTE (DEVICE(4:4:4))))</TIMING></FMFTIME><FMFTIME>IDT72t4098L5BB<SOURCE>Integrated Device Technology DSC-5995/9, September 2004</SOURCE><COMMENT>The Values listed are for VCC=2.375V to 2.625V, CL=10pF, Ta=0 to 70CFor each parameter only minimum or maximum values were provided by the vendor, other values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH RCLK Q0 (0.6:2.1:3.6) (0.6:2.1:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH OENeg Q0 (1.2:2.4:3.6) (1.2:2.4:3.6) (1.2:2.4:3.6) (0) (1.2:2.4:3.6) (0))    (IOPATH MRSNeg EFNeg (4:8:12) (4:8:12))    (IOPATH WCLK FFNeg (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH RCLK EFNeg (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH WCLK PAFNeg (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH RCLK PAENeg (1.2:2.4:3.6) (1.2:2.4:3.6))    (IOPATH RCLK ERCLK (1.3:2.6:4.0) (1.3:2.6:4.0))    (IOPATH RCLK ERENNeg (1.2:2.4:3.6) (1.2:2.4:3.6))  ))  (TIMINGCHECK    (SETUP D0 WCLK (1.5:1.5:1.5))    (SETUP RENNeg RCLK (1.5:1.5:1.5))    (SETUP WCSNeg WCLK (1.5:1.5:1.5))    (SETUP SI SCLK (15:15:15))    (SETUP SENNeg SCLK (5:5:5))    (SETUP RENNeg MRSNeg (15:15:15))    (SETUP HSTL MRSNeg (4:4:4))    (HOLD D0 WCLK (0.5:0.5:0.5))    (HOLD RENNeg RCLK (.5:.5:.5))    (HOLD WCSNeg WCLK (.5:.5:.5))    (HOLD SI SCLK (5:5:5))    (HOLD SENNeg SCLK (5:5:5))    (RECOVERY RENNeg MRSNeg (10:10:10))    (WIDTH (negedge MRSNeg) (30:30:30))    (WIDTH (COND SDR (negedge RCLK)) (2.3:2.3:2.3))    (WIDTH (COND SDR (posedge RCLK)) (2.3:2.3:2.3))    (WIDTH (COND DDR (negedge RCLK)) (4.5:4.5:4.5))    (WIDTH (COND DDR (posedge RCLK)) (4.5:4.5:4.5))    (WIDTH (negedge SCLK) (45:45:45))    (WIDTH (posedge SCLK) (45:45:45))    (PERIOD (COND SDR (posedge RCLK)) (5:5:5))    (PERIOD (COND DDR (posedge RCLK)) (10:10:10))    (PERIOD (posedge SCLK) (100:100:100))  ))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE (DEVICE(4:4:4)))))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE (DEVICE(4:4:4)))))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW3) (DELAY (ABSOLUTE (DEVICE(5:5:5))))</TIMING></FMFTIME><FMFTIME>IDT72t4098L6-7BB<SOURCE>Integrated Device Technology DSC-5995/9, September 2004</SOURCE>IDT72t4098L6-7BBI<SOURCE>Integrated Device Technology DSC-5995/9, September 2004</SOURCE><COMMENT>The Values listed are for VCC=2.375V to 2.625V, CL=10pF, Ta=0 to 70C (Ta=-45 to 80C for 6-7BBI)For each parameter only minimum or maximum values were provided by the vendor, other values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH RCLK Q0 (0.6:2.2:3.8) (0.6:2.2:3.8) (1.2:2.5:3.8) (1.2:2.5:3.8) (1.2:2.5:3.8) (1.2:2.5:3.8))    (IOPATH OENeg Q0 (1.2:2.5:3.8) (1.2:2.5:3.8) (1.2:2.5:3.8) (0) (1.2:2.5:3.8) (0))    (IOPATH MRSNeg EFNeg (5:10:15) (5:10:15))    (IOPATH WCLK FFNeg (1.2:2.5:3.8) (1.2:2.5:3.8))    (IOPATH RCLK EFNeg (1.2:2.5:3.8) (1.2:2.5:3.8))    (IOPATH WCLK PAFNeg (1.2:2.5:3.8) (1.2:2.5:3.8))    (IOPATH RCLK PAENeg (1.2:2.5:3.8) (1.2:2.5:3.8))    (IOPATH RCLK ERCLK (1.4:2.8:4.3) (1.4:2.8:4.3))    (IOPATH RCLK ERENNeg (1.2:2.5:3.8) (1.2:2.5:3.8))  ))  (TIMINGCHECK    (SETUP D0 WCLK (2:2:2))    (SETUP RENNeg RCLK (2:2:2))    (SETUP WCSNeg WCLK (2:2:2))    (SETUP SI SCLK (15:15:15))    (SETUP SENNeg SCLK (5:5:5))    (SETUP RENNeg MRSNeg (15:15:15))    (SETUP HSTL MRSNeg (4:4:4))    (HOLD D0 WCLK (0.5:0.5:0.5))    (HOLD RENNeg RCLK (.5:.5:.5))    (HOLD WCSNeg WCLK (.5:.5:.5))    (HOLD SI SCLK (5:5:5))    (HOLD SENNeg SCLK (5:5:5))    (RECOVERY RENNeg MRSNeg (10:10:10))    (WIDTH (negedge MRSNeg) (30:30:30))    (WIDTH (COND SDR (negedge RCLK)) (2.8:2.8:2.8))    (WIDTH (COND SDR (posedge RCLK)) (2.8:2.8:2.8))    (WIDTH (COND DDR (negedge RCLK)) (6:6:6))    (WIDTH (COND DDR (posedge RCLK)) (6:6:6))    (WIDTH (negedge SCLK) (45:45:45))    (WIDTH (posedge SCLK) (45:45:45))    (PERIOD (COND SDR (posedge RCLK)) (6.7:6.7:6.7))    (PERIOD (COND DDR (posedge RCLK)) (13:13:13))    (PERIOD (posedge SCLK) (100:100:100))  ))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE (DEVICE(5:5:5)))))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE (DEVICE(5:5:5)))))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW3) (DELAY (ABSOLUTE (DEVICE(6:6:6))))</TIMING></FMFTIME><FMFTIME>IDT72t4098L10BB<SOURCE>Integrated Device Technology DSC-5995/9, September 2004</SOURCE><COMMENT>The Values listed are for VCC=2.375V to 2.625V, CL=10pF, Ta=0 to 70CFor each parameter only minimum or maximum values were provided by the vendor, other values are derived</COMMENT><TIMING>  (DELAY (ABSOLUTE    (IOPATH RCLK Q0 (0.6:2.5:4.5) (0.6:2.5:4.5) (1.5:3.0:4.5) (1.5:3.0:4.5) (1.5:3.0:4.5) (1.5:3.0:4.5))    (IOPATH OENeg Q0 (1.5:3.0:4.5) (1.5:3.0:4.5) (1.5:3.0:4.5) (0) (1.5:3.0:4.5) (0))    (IOPATH MRSNeg EFNeg (5:10:15) (5:10:15))    (IOPATH WCLK FFNeg (1.5:3.0:4.5) (1.5:3.0:4.5))    (IOPATH RCLK EFNeg (1.5:3.0:4.5) (1.5:3.0:4.5))    (IOPATH WCLK PAFNeg (1.5:3.0:4.5) (1.5:3.0:4.5))    (IOPATH RCLK PAENeg (1.5:3.0:4.5) (1.5:3.0:4.5))    (IOPATH RCLK ERCLK (1.7:3.4:5) (1.7:3.4:5))    (IOPATH RCLK ERENNeg (1.5:3.0:4.5) (1.5:3.0:4.5))  ))  (TIMINGCHECK    (SETUP D0 WCLK (3:3:3))    (SETUP RENNeg RCLK (3:3:3))    (SETUP WCSNeg WCLK (3:3:3))    (SETUP SI SCLK (15:15:15))    (SETUP SENNeg SCLK (5:5:5))    (SETUP RENNeg MRSNeg (15:15:15))    (SETUP HSTL MRSNeg (4:4:4))    (HOLD D0 WCLK (0.5:0.5:0.5))    (HOLD RENNeg RCLK (.5:.5:.5))    (HOLD WCSNeg WCLK (.5:.5:.5))    (HOLD SI SCLK (5:5:5))    (HOLD SENNeg SCLK (5:5:5))    (RECOVERY RENNeg MRSNeg (10:10:10))    (WIDTH (negedge MRSNeg) (30:30:30))    (WIDTH (COND SDR (negedge RCLK)) (4.5:4.5:4.5))    (WIDTH (COND SDR (posedge RCLK)) (4.5:4.5:4.5))    (WIDTH (COND DDR (negedge RCLK)) (9.5:9.5:9.5))    (WIDTH (COND DDR (posedge RCLK)) (9.5:9.5:9.5))    (WIDTH (negedge SCLK) (45:45:45))    (WIDTH (posedge SCLK) (45:45:45))    (PERIOD (COND SDR (posedge RCLK)) (10:10:10))    (PERIOD (COND DDR (posedge RCLK)) (20:20:20))    (PERIOD (posedge SCLK) (100:100:100))  ))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW1) (DELAY (ABSOLUTE (DEVICE(7:7:7)))))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW2) (DELAY (ABSOLUTE (DEVICE(7:7:7)))))  (CELL (CELLTYPE "VITALbuf")    (INSTANCE %LABEL%/SKEW3) (DELAY (ABSOLUTE (DEVICE(8:8:8))))</TIMING></FMFTIME></BODY></FTML>
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