idt723643.vhd

VHDL的ram和fifo model code 包含众多的厂家

          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_ENB_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_ENB_CLKB);

      -- MBB/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MBB,
          TestSignalName  => "MBB",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MBB_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_MBB_CLKB);

      -- ENB/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => ENB,
          TestSignalName  => "ENB",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_ENB_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_ENB_CLKB);

      -- MBB/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MBB,
          TestSignalName  => "MBB",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tENS,
          SetupLow        => tENS,
          HoldHigh        => tENH,
          HoldLow         => tENH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MBB_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_MBB_CLKB);

      -- MRSNeg/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MRSNeg,
          TestSignalName  => "MRSNeg",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tRSTS,
          SetupLow        => tRSTS,
          HoldHigh        => tRSTH,
          HoldLow         => tRSTH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MRSNeg_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_MRSNeg_CLKA);

      -- MRSNeg/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => MRSNeg,
          TestSignalName  => "MRSNeg",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tRSTS,
          SetupLow        => tRSTS,
          HoldHigh        => tRSTH,
          HoldLow         => tRSTH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_MRSNeg_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_MRSNeg_CLKB);

      -- PRSNeg/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => PRSNeg,
          TestSignalName  => "PRSNeg",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tRSTS,
          SetupLow        => tRSTS,
          HoldHigh        => tRSTH,
          HoldLow         => tRSTH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_PRSNeg_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_PRSNeg_CLKA);

      -- PRSNeg/CLKB setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => PRSNeg,
          TestSignalName  => "PRSNeg",
          RefSignal       => CLKB,
          RefSignalName   => "CLKB",
          SetupHigh       => tRSTS,
          SetupLow        => tRSTS,
          HoldHigh        => tRSTH,
          HoldLow         => tRSTH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_PRSNeg_CLKB,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_PRSNeg_CLKB);

      -- FS0SD/MRSNeg setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => FS0SD,
          TestSignalName  => "FS0SD",
          RefSignal       => MRSNeg,
          RefSignalName   => "MRSNeg",
          SetupHigh       => tFSS,
          SetupLow        => tFSS,
          HoldHigh        => tFSH,
          HoldLow         => tFSH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_FS0SD_MRSNeg,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_FS0SD_MRSNeg);

      -- FS1SEN/MRSNeg setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => FS1SEN,
          TestSignalName  => "FS1SEN",
          RefSignal       => MRSNeg,
          RefSignalName   => "MRSNeg",
          SetupHigh       => tFSS,
          SetupLow        => tFSS,
          HoldHigh        => tFSH,
          HoldLow         => tFSH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_FS1SEN_MRSNeg,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_FS1SEN_MRSNeg);

      -- BEFWFT/MRSNeg setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => BEFWFT,
          TestSignalName  => "BEFWFT",
          RefSignal       => MRSNeg,
          RefSignalName   => "MRSNeg",
          SetupHigh       => tBES,
          SetupLow        => tBES,
          HoldHigh        => tBEH,
          HoldLow         => tBEH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_BEFWFT_MRSNeg,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_BEFWFT_MRSNeg);

      -- SPMNeg/MRSNeg setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => SPMNeg,
          TestSignalName  => "SPMNeg",
          RefSignal       => MRSNeg,
          RefSignalName   => "MRSNeg",
          SetupHigh       => tSPMS,
          SetupLow        => tSPMS,
          HoldHigh        => tSPMH,
          HoldLow         => tSPMH,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_SPMNeg_MRSNeg,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_SPMNeg_MRSNeg);

      -- FS0SD/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => FS0SD,
          TestSignalName  => "FS0SD",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tSDS,
          SetupLow        => tSDS,
          HoldHigh        => tSDH,
          HoldLow         => tSDH,
          CheckEnabled    => Offs_Ser_Load_Modeint = '1',
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_FS0SD_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_FS0SD_CLKA);

      -- FS1SEN/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => FS1SEN,
          TestSignalName  => "FS1SEN",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tSENS,
          SetupLow        => tSENS,
          HoldHigh        => tSENH,
          HoldLow         => tSENH,
          CheckEnabled    => Offs_Ser_Load_Modeint = '1',
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_FS1SEN_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_FS1SEN_CLKA);

      -- BEFWFT/CLKA setup/hold time check

      VitalSetupHoldCheck (
          TestSignal      => BEFWFT,
          TestSignalName  => "BEFWFT",
          RefSignal       => CLKA,
          RefSignalName   => "CLKA",
          SetupHigh       => tFWS,
          SetupLow        => tFWS,
          CheckEnabled    => True,
          RefTransition   => '/',
          HeaderMsg       => InstancePath & partID,
          TimingData      => TD_BEFWFT_CLKA,
          XOn             => XOn,
          MsgOn           => MsgOn,
          Violation       => Tviol_BEFWFT_CLKA);

  Violation := Pviol_CLKA          	OR
               Pviol_CLKB          	OR
               Tviol_A0_CLKA       	OR
               TViol_B0_CLKB       	OR
               Tviol_CSANeg_CLKA   	OR
               Tviol_WRA_CLKA      	OR
               Tviol_ENA_CLKA      	OR
               Tviol_MBA_CLKA      	OR      
               Tviol_CSBNeg_CLKB   	OR
               Tviol_WRB_CLKB      	OR
               Tviol_ENB_CLKB        	OR
               Tviol_MBB_CLKB       	OR
               Tviol_MRSNeg_CLKA      	OR
               Tviol_MRSNeg_CLKB      	OR
               Tviol_PRSNeg_CLKA        OR
               Tviol_PRSNeg_CLKB        OR
               Tviol_FS0SD_MRSNeg       OR
               Tviol_FS1SEN_MRSNeg      OR
               Tviol_BEFWFT_MRSNeg      OR
               Tviol_SPMNeg_MRSNeg      OR
               Tviol_FS0SD_CLKA     	OR
               Tviol_FS1SEN_CLKA	OR
               Tviol_BEFWFT_CLKA;
               
                ASSERT   Violation = '0'
                REPORT   InstancePath & partID & " : signal values may be" &
                         " incorret due timing violation(s)"
                SEVERITY Warning;
  END IF;
  
END PROCESS TimingChecks;

--------------------------------------------------------------------------------
-- Functionality Section                                                      --
--------------------------------------------------------------------------------

  ------------------------------------------------------------------------------
  -- Reset 
  ------------------------------------------------------------------------------
  -- Initial Master Reset - MRSNeg and MRS2 should be LOW
  ------------------------------------------------------------------------------
  
  Init_MReset: PROCESS (MRSNeg)
  BEGIN
    IF (MRSNeg = '0') THEN
       MRSDoneint <= '1';
    END IF;
  END