idt723643.vhd

VHDL的ram和fifo model code 包含众多的厂家

    FFIR     : OUT   std_logic := 'U';
    FS0SD    : IN    std_logic := 'X'; 
    FS1SEN   : IN    std_logic := 'X'; 
    MBA      : IN    std_logic := 'X';
    MBB      : IN    std_logic := 'X';
    MBF1Neg  : OUT   std_logic := 'U';
    MBF2Neg  : OUT   std_logic := 'U';
    MRSNeg   : IN    std_logic := 'X'; 
    PRSNeg   : IN    std_logic := 'X'; 
    SIZE     : IN    std_logic := 'X'; 
    SPMNeg   : IN    std_logic := 'X';
    WRA      : IN    std_logic := 'X';  
    WRB      : IN    std_logic := 'X'  
     );
   PORT MAP (
    A_ipd(0)    => A0_ipd,
    A_ipd(1)    => A1_ipd,
    A_ipd(2)    => A2_ipd,
    A_ipd(3)    => A3_ipd,
    A_ipd(4)    => A4_ipd,
    A_ipd(5)    => A5_ipd,
    A_ipd(6)    => A6_ipd,
    A_ipd(7)    => A7_ipd,
    A_ipd(8)    => A8_ipd,
    A_ipd(9)    => A9_ipd,
    A_ipd(10)   => A10_ipd,
    A_ipd(11)   => A11_ipd,
    A_ipd(12)   => A12_ipd,
    A_ipd(13)   => A13_ipd,
    A_ipd(14)   => A14_ipd,
    A_ipd(15)   => A15_ipd,
    A_ipd(16)   => A16_ipd,
    A_ipd(17)   => A17_ipd,
    A_ipd(18)   => A18_ipd,
    A_ipd(19)   => A19_ipd,
    A_ipd(20)   => A20_ipd,
    A_ipd(21)   => A21_ipd,
    A_ipd(22)   => A22_ipd,
    A_ipd(23)   => A23_ipd,
    A_ipd(24)   => A24_ipd,
    A_ipd(25)   => A25_ipd,
    A_ipd(26)   => A26_ipd,
    A_ipd(27)   => A27_ipd,
    A_ipd(28)   => A28_ipd,
    A_ipd(29)   => A29_ipd,
    A_ipd(30)   => A30_ipd,
    A_ipd(31)   => A31_ipd,
    A_ipd(32)   => A32_ipd,
    A_ipd(33)   => A33_ipd,
    A_ipd(34)   => A34_ipd,
    A_ipd(35)   => A35_ipd,
    A(0)    	=> A0,
    A(1)    	=> A1,
    A(2)    	=> A2,
    A(3)    	=> A3,
    A(4) 	=> A4,
    A(5)  	=> A5,
    A(6)  	=> A6,
    A(7)    	=> A7,
    A(8)    	=> A8,
    A(9)    	=> A9,
    A(10)   	=> A10,
    A(11)   	=> A11,
    A(12)   	=> A12,
    A(13)   	=> A13,
    A(14)   	=> A14,
    A(15)   	=> A15,
    A(16)   	=> A16,
    A(17)   	=> A17,
    A(18)   	=> A18,
    A(19)   	=> A19,
    A(20)   	=> A20,
    A(21)   	=> A21,
    A(22)   	=> A22,
    A(23)   	=> A23,
    A(24)   	=> A24,
    A(25)   	=> A25,
    A(26)   	=> A26,
    A(27)   	=> A27,
    A(28)   	=> A28,
    A(29)   	=> A29,
    A(30)   	=> A30,
    A(31)   	=> A31,
    A(32)   	=> A32,
    A(33)   	=> A33,
    A(34)   	=> A34,
    A(35)    	=> A35,
    AENeg   	=> AENeg,
    AFNeg   	=> AFNeg,
    B_ipd(0)    => B0_ipd,
    B_ipd(1)    => B1_ipd,
    B_ipd(2)    => B2_ipd,
    B_ipd(3)    => B3_ipd,
    B_ipd(4)    => B4_ipd,
    B_ipd(5)    => B5_ipd,
    B_ipd(6)    => B6_ipd,
    B_ipd(7)    => B7_ipd,
    B_ipd(8)    => B8_ipd,
    B_ipd(9)    => B9_ipd,
    B_ipd(10)   => B10_ipd,
    B_ipd(11)   => B11_ipd,
    B_ipd(12)   => B12_ipd,
    B_ipd(13)   => B13_ipd,
    B_ipd(14)   => B14_ipd,
    B_ipd(15)   => B15_ipd,
    B_ipd(16)   => B16_ipd,
    B_ipd(17)   => B17_ipd,
    B_ipd(18)   => B18_ipd,
    B_ipd(19)   => B19_ipd,
    B_ipd(20)   => B20_ipd,
    B_ipd(21)   => B21_ipd,
    B_ipd(22)   => B22_ipd,
    B_ipd(23)   => B23_ipd,
    B_ipd(24)   => B24_ipd,
    B_ipd(25)   => B25_ipd,
    B_ipd(26)   => B26_ipd,
    B_ipd(27)   => B27_ipd,
    B_ipd(28)   => B28_ipd,
    B_ipd(29)   => B29_ipd,
    B_ipd(30)   => B30_ipd,
    B_ipd(31)   => B31_ipd,
    B_ipd(32)   => B32_ipd,
    B_ipd(33)   => B33_ipd,
    B_ipd(34)   => B34_ipd,
    B_ipd(35)   => B35_ipd,
    B(0)    	=> B0,
    B(1)    	=> B1,
    B(2)    	=> B2,
    B(3)    	=> B3,
    B(4) 	=> B4,
    B(5)  	=> B5,
    B(6)  	=> B6,
    B(7)    	=> B7,
    B(8)    	=> B8,
    B(9)    	=> B9,
    B(10)   	=> B10,
    B(11)   	=> B11,
    B(12)   	=> B12,
    B(13)   	=> B13,
    B(14)   	=> B14,
    B(15)   	=> B15,
    B(16)   	=> B16,
    B(17)   	=> B17,
    B(18)   	=> B18,
    B(19)   	=> B19,
    B(20)   	=> B20,
    B(21)   	=> B21,
    B(22)   	=> B22,
    B(23)   	=> B23,
    B(24)   	=> B24,
    B(25)   	=> B25,
    B(26)   	=> B26,
    B(27)   	=> B27,
    B(28)   	=> B28,
    B(29)   	=> B29,
    B(30)   	=> B30,
    B(31)   	=> B31,
    B(32)   	=> B32,
    B(33)   	=> B33,
    B(34)   	=> B34,
    B(35)    	=> B35,
    BEFWFT   	=> BEFWFT_ipd,
    BM   	=> BM_ipd,
    CLKA        => CLKA_ipd,
    CLKB        => CLKB_ipd,
    CSANeg      => CSANeg_ipd,
    CSBNeg      => CSBNeg_ipd,
    EFOR   	=> EFOR,
    ENA         => ENA_ipd,
    ENB         => ENB_ipd,
    FFIR   	=> FFIR,
    FS0SD       => FS0SD_ipd,
    FS1SEN      => FS1SEN_ipd,
    MBA         => MBA_ipd,
    MBB         => MBB_ipd,
    MBF1Neg     => MBF1Neg,
    MBF2Neg     => MBF2Neg,
    MRSNeg      => MRSNeg_ipd,
    PRSNeg      => PRSNeg_ipd,
    SIZE        => SIZE_ipd,
    SPMNeg      => SPMNeg_ipd,
    WRA         => WRA_ipd,
    WRB         => WRB_ipd);
    
  -- zero delayed outputs and bidirectional ports 
  -- (func. sec. uses these signals instead of =
  --  actual outputs and bidirectional ports);
  -- actual outputs are assigned in Path Delay Section
  
  SIGNAL A_zd         : std_logic_vector (35 downto 0);
  SIGNAL B_zd         : std_logic_vector (35 downto 0); 
  SIGNAL AENeg_zd    : std_logic;  
  SIGNAL AFNeg_zd    : std_logic;  
  SIGNAL EFOR_zd    : std_logic;     
  SIGNAL FFIR_zd    : std_logic;     
  SIGNAL MBF1Neg_zd   : std_logic;    
  SIGNAL MBF2Neg_zd   : std_logic;   

  ------------------------------------------------------------------------------
  -- FIFO memory definitions
  ------------------------------------------------------------------------------
  -- general
  CONSTANT FIFOWordLength  :  positive := 36;
  SUBTYPE  FIFOWord    IS std_logic_vector(FIFOWordLength - 1 DOWNTO 0);
  TYPE     FIFOArray   IS ARRAY (0 TO FIFOSize - 1) OF FIFOWord;
  
  CONSTANT MailWordLength  :  positive := 36;
  SUBTYPE  MailWord    IS std_logic_vector(MailWordLength - 1 DOWNTO 0);
  
  CONSTANT Offs_Par_Number :  positive := 2; -- Number of Words while
  					     -- Parallel Offset Loading
  CONSTANT Offs_Ser_Number :  positive := OffsetSize*2; -- Number of Bits while
  					     -- Serial Offset Loading
  
  -- special
  CONSTANT FIFOWordBytes   :  positive := 4;
  
  ------------------------------------------------------------------------------
  -- internal constants 
  ------------------------------------------------------------------------------
  
     CONSTANT SIZByte : std_logic := '1';	
     CONSTANT SIZWord : std_logic := '0';    
  
  ------------------------------------------------------------------------------
  -- internal signals 
  ------------------------------------------------------------------------------
  -- FIFO Arrays
  
     SIGNAL FIFOMemory1int : FIFOArray := (FIFOArray'range =>
                                        FIFOWord'(OTHERS => 'X'));
                                        
  -- Main Registers                                       
     -- Input Registers
      
     SIGNAL InputReg1int   : FIFOWord := (OTHERS => 'X');
     
     -- Output Registers
      
     SIGNAL OutputReg1int  : FIFOWord := (OTHERS => 'X');
     
     -- FIFO Pointers
     
     SIGNAL ReadPtr1int    : Natural RANGE 0 TO FIFOSize-1;
     SIGNAL WritePtr1int   : Natural RANGE 0 TO FIFOSize-1;
     
     SIGNAL ReadPtr1int_add : std_logic;
                            -- additional high bits to differ cases when
     SIGNAL WritePtr1int_add : std_logic; -- FIFO empty or full
     
     -- FIFO Offset for Almoust Empty/Full Flags
     
     SIGNAL X1int, Y1int   : Natural RANGE 0 TO FIFOSize-1;
     
     -- Mail Registers
     
     SIGNAL Mail1int,
            Mail2int       : MailWord := (OTHERS => 'X');
            
     -- Flags for Standart and FWFT mode
     
     SIGNAL EFNegint, FFNegint,  	-- standard mode 
     	    ORint			-- FWFT mode
     	    : std_ulogic;    

     -- Flags Flip-flop first stage (each flag is synchonized 
     -- to its Port Clock through two flip-flop stages)
     
     SIGNAL EF1int, FF1int, AE1int, AF1int : std_ulogic;
      
     ---------- Input Registers Controlling Signals ------------      
     -- Flags "Input Register is loaded" - in this 
     -- model they will be loaded to FIFOMemory on CLK negedge      
     SIGNAL InputReg1Readyint   : std_ulogic; 
     
     ---------- Output Registers Controlling Signals ------------      
     SIGNAL OutputReg1Readyint : std_ulogic; -- all 4-bytes have been
     				 	    -- read to Port-B 
     SIGNAL OutputReg1ReadyNextint : std_ulogic;
                                            -- all 4-bytes will be 
     				 	    -- read to Port-B next CLKB
     				 	    -- posedge
     -- Pointers for Byte/Word Access for PortB
        
     SIGNAL OutputReg1Ptrint : Natural RANGE 0 TO FIFOWordBytes-1;
     
       -- Pointers for Byte/Word Access that will be latched on CLKB posedge
       	     						   
       SIGNAL OutputReg1PtrNextint   : Natural RANGE 0 TO FIFOWordBytes - 1;
         
     SIGNAL FWFTFirst : std_ulogic; -- first word though in FWFT mode
     
     -------------------------------------------------------------------------  
     -- Master Reset 1,2 / Partial Reset 1,2
     
     SIGNAL RST1int: std_ulogic; -- MRSNeg AND PRSNeg; MRS2Neg AND PRS2Neg
     
     -- Master Reset (MRSNeg = '0' done
     
     SIGNAL MRSDoneint: std_ulogic := '0';
     
     -- Counters of Clocks during Master/Partion Reset is active or just after
     -- Reset
     
     SIGNAL CountCLKA1int, CountCLKB1int: Natural;
     
     -- Big Endian ('1') / Little Endian ('0') Mode
     
     SIGNAL BEint: std_ulogic;
     
     -- Internal Control Signals
     
     SIGNAL EnWrFIFO1int, EnRdFIFO1int, 
     	    EnWrMail1int, EnRdMail1int, EnWrMail2int, EnRdMail2int: std_ulogic; 
     	    
     ---------------------------------------------------------------------------
     -- ALmost-Empty/Almost-Full Offsets Loading Mode
     
     SIGNAL Offs_Par_Load_Modeint : std_ulogic := '0'; -- Parallel Offsets Loading Mode
     SIGNAL Offs_Ser_Load_Modeint : std_ulogic := '0'; -- Serial Offsets Loading Mode
     
     -- Word/Bit Counter while Offset Loading
     
     SIGNAL CountLoadOffsetint: Natural; 
     
     ---------------------------------------------------------------------------
     -- Additional Signals