📄 idt723643.vhd
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---------------------------------------------------------------------------------- File name : IDT723643.vhd--------------------------------------------------------------------------------- Copyright (C) 1998 Integrated Device Technology; http://www.idt.com/-- Developed by SEVA Technologies Inc. (Moscow branch) under contract to IDT-- and supported by Free Model Foundry; http://www.FreeModelFoundry.com---- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.---- This VHDL model is provided on an "AS IS" basis and IDT makes absolutely no-- warranty with respect to the information contained herein. IDT DISCLAIMS-- AND CUSTOMER WAIVES ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE-- ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE USER ACCORDINGLY, IN-- NO EVENT SHALL IDT BE LIABLE FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN-- CONTRACT OR TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL,-- CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR-- APPLICATION OF THE VHDL model. Further, IDT reserves the right to make-- changes without notice to any product herein to improve reliability,-- function, or design. IDT does not convey any license under patent rights-- or any other intellectual property rights, including those of third parties.-- IDT is not obligated to provide maintenance or support for the licensed VHDL-- model.---- MODIFICATION HISTORY :---- version | author | mod date: | changes made-- V1.0 | Anatoli Sokhatski | 98 OCT 06 | initial release-- V1.1 | R. Munden | 02 MAY 19 | licensing changed to GPL----------------------------------------------------------------------------------- PART DESCRIPTION :---- Library: FIFO-- Technology: CMOS-- Part: IDT723643---- Descripton: SyncFIFO With Bus-Matching 1024x36--------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.vital_primitives.ALL; USE ieee.vital_timing.ALL;LIBRARY fmf; USE fmf.ff_package.ALL; USE fmf.gen_utils.ALL; USE fmf.conversions.to_nat; USE fmf.conversions.to_slv;---------------------------------------------------------------------------------- ENTITY DECLARATION ----------------------------------------------------------------------------------ENTITY IDT723643 IS GENERIC ( ---------------------------------------------------------------------------- -- VITAL generics ---------------------------------------------------------------------------- -- tipd delays: interconnect path delays -- (there must be one generic for each input pin) tipd_A0 : VitalDelayType01 := VitalZeroDelay01; tipd_A1 : VitalDelayType01 := VitalZeroDelay01; tipd_A2 : VitalDelayType01 := VitalZeroDelay01; tipd_A3 : VitalDelayType01 := VitalZeroDelay01; tipd_A4 : VitalDelayType01 := VitalZeroDelay01; tipd_A5 : VitalDelayType01 := VitalZeroDelay01; tipd_A6 : VitalDelayType01 := VitalZeroDelay01; tipd_A7 : VitalDelayType01 := VitalZeroDelay01; tipd_A8 : VitalDelayType01 := VitalZeroDelay01; tipd_A9 : VitalDelayType01 := VitalZeroDelay01; tipd_A10 : VitalDelayType01 := VitalZeroDelay01; tipd_A11 : VitalDelayType01 := VitalZeroDelay01; tipd_A12 : VitalDelayType01 := VitalZeroDelay01; tipd_A13 : VitalDelayType01 := VitalZeroDelay01; tipd_A14 : VitalDelayType01 := VitalZeroDelay01; tipd_A15 : VitalDelayType01 := VitalZeroDelay01; tipd_A16 : VitalDelayType01 := VitalZeroDelay01; tipd_A17 : VitalDelayType01 := VitalZeroDelay01; tipd_A18 : VitalDelayType01 := VitalZeroDelay01; tipd_A19 : VitalDelayType01 := VitalZeroDelay01; tipd_A20 : VitalDelayType01 := VitalZeroDelay01; tipd_A21 : VitalDelayType01 := VitalZeroDelay01; tipd_A22 : VitalDelayType01 := VitalZeroDelay01; tipd_A23 : VitalDelayType01 := VitalZeroDelay01; tipd_A24 : VitalDelayType01 := VitalZeroDelay01; tipd_A25 : VitalDelayType01 := VitalZeroDelay01; tipd_A26 : VitalDelayType01 := VitalZeroDelay01; tipd_A27 : VitalDelayType01 := VitalZeroDelay01; tipd_A28 : VitalDelayType01 := VitalZeroDelay01; tipd_A29 : VitalDelayType01 := VitalZeroDelay01; tipd_A30 : VitalDelayType01 := VitalZeroDelay01; tipd_A31 : VitalDelayType01 := VitalZeroDelay01; tipd_A32 : VitalDelayType01 := VitalZeroDelay01; tipd_A33 : VitalDelayType01 := VitalZeroDelay01; tipd_A34 : VitalDelayType01 := VitalZeroDelay01; tipd_A35 : VitalDelayType01 := VitalZeroDelay01; tipd_B0 : VitalDelayType01 := VitalZeroDelay01; tipd_B1 : VitalDelayType01 := VitalZeroDelay01; tipd_B2 : VitalDelayType01 := VitalZeroDelay01; tipd_B3 : VitalDelayType01 := VitalZeroDelay01; tipd_B4 : VitalDelayType01 := VitalZeroDelay01; tipd_B5 : VitalDelayType01 := VitalZeroDelay01; tipd_B6 : VitalDelayType01 := VitalZeroDelay01; tipd_B7 : VitalDelayType01 := VitalZeroDelay01; tipd_B8 : VitalDelayType01 := VitalZeroDelay01; tipd_B9 : VitalDelayType01 := VitalZeroDelay01; tipd_B10 : VitalDelayType01 := VitalZeroDelay01; tipd_B11 : VitalDelayType01 := VitalZeroDelay01; tipd_B12 : VitalDelayType01 := VitalZeroDelay01; tipd_B13 : VitalDelayType01 := VitalZeroDelay01; tipd_B14 : VitalDelayType01 := VitalZeroDelay01; tipd_B15 : VitalDelayType01 := VitalZeroDelay01; tipd_B16 : VitalDelayType01 := VitalZeroDelay01; tipd_B17 : VitalDelayType01 := VitalZeroDelay01; tipd_B18 : VitalDelayType01 := VitalZeroDelay01; tipd_B19 : VitalDelayType01 := VitalZeroDelay01; tipd_B20 : VitalDelayType01 := VitalZeroDelay01; tipd_B21 : VitalDelayType01 := VitalZeroDelay01; tipd_B22 : VitalDelayType01 := VitalZeroDelay01; tipd_B23 : VitalDelayType01 := VitalZeroDelay01; tipd_B24 : VitalDelayType01 := VitalZeroDelay01; tipd_B25 : VitalDelayType01 := VitalZeroDelay01; tipd_B26 : VitalDelayType01 := VitalZeroDelay01; tipd_B27 : VitalDelayType01 := VitalZeroDelay01; tipd_B28 : VitalDelayType01 := VitalZeroDelay01; tipd_B29 : VitalDelayType01 := VitalZeroDelay01; tipd_B30 : VitalDelayType01 := VitalZeroDelay01; tipd_B31 : VitalDelayType01 := VitalZeroDelay01; tipd_B32 : VitalDelayType01 := VitalZeroDelay01; tipd_B33 : VitalDelayType01 := VitalZeroDelay01; tipd_B34 : VitalDelayType01 := VitalZeroDelay01; tipd_B35 : VitalDelayType01 := VitalZeroDelay01; tipd_BEFWFT : VitalDelayType01 := VitalZeroDelay01; tipd_BM : VitalDelayType01 := VitalZeroDelay01; tipd_CLKA : VitalDelayType01 := VitalZeroDelay01; tipd_CLKB : VitalDelayType01 := VitalZeroDelay01; tipd_CSANeg : VitalDelayType01 := VitalZeroDelay01; tipd_CSBNeg : VitalDelayType01 := VitalZeroDelay01; tipd_ENA : VitalDelayType01 := VitalZeroDelay01; tipd_ENB : VitalDelayType01 := VitalZeroDelay01; tipd_FS0SD : VitalDelayType01 := VitalZeroDelay01; tipd_FS1SEN : VitalDelayType01 := VitalZeroDelay01; tipd_MBA : VitalDelayType01 := VitalZeroDelay01; tipd_MBB : VitalDelayType01 := VitalZeroDelay01; tipd_MRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_PRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SIZE : VitalDelayType01 := VitalZeroDelay01; tipd_SPMNeg : VitalDelayType01 := VitalZeroDelay01; tipd_WRA : VitalDelayType01 := VitalZeroDelay01; tipd_WRB : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays -- tA tpd_CLKA_A0 : VitalDelayType01 := UnitDelay01; tpd_CLKB_B0 : VitalDelayType01 := UnitDelay01; -- tWFF tpd_CLKA_FFIR : VitalDelayType01 := UnitDelay01; -- tREF tpd_CLKB_EFOR : VitalDelayType01 := UnitDelay01; -- tPAE tpd_CLKB_AENeg : VitalDelayType01 := UnitDelay01; -- tPAF tpd_CLKA_AFNeg : VitalDelayType01 := UnitDelay01; -- tPMF tpd_CLKA_MBF1Neg : VitalDelayType01 := UnitDelay01; tpd_CLKA_MBF2Neg : VitalDelayType01 := UnitDelay01; tpd_CLKB_MBF1Neg : VitalDelayType01 := UnitDelay01; tpd_CLKB_MBF2Neg : VitalDelayType01 := UnitDelay01; -- tPMR tpd_CLKA_B0 : VitalDelayType01 := UnitDelay01; tpd_CLKB_A0 : VitalDelayType01 := UnitDelay01; -- tMDV tpd_MBA_A0 : VitalDelayType01 := UnitDelay01; tpd_MBB_B0 : VitalDelayType01 := UnitDelay01; -- tRSF tpd_MRSNeg_AENeg : VitalDelayType01 := UnitDelay01; tpd_MRSNeg_AFNeg : VitalDelayType01 := UnitDelay01; tpd_MRSNeg_MBF1Neg : VitalDelayType01 := UnitDelay01; tpd_MRSNeg_MBF2Neg : VitalDelayType01 := UnitDelay01; tpd_PRSNeg_AENeg : VitalDelayType01 := UnitDelay01; tpd_PRSNeg_AFNeg : VitalDelayType01 := UnitDelay01; tpd_PRSNeg_MBF1Neg : VitalDelayType01 := UnitDelay01; tpd_PRSNeg_MBF2Neg : VitalDelayType01 := UnitDelay01; -- tEN/tDIS tpd_CSANeg_A0 : VitalDelayType01Z := UnitDelay01Z; tpd_WRA_A0 : VitalDelayType01Z := UnitDelay01Z; tpd_CSBNeg_B0 : VitalDelayType01Z := UnitDelay01Z; tpd_WRB_B0 : VitalDelayType01Z := UnitDelay01Z; -- tpw values: pulse widths -- tCLK tperiod_CLKA_posedge : VitalDelayType := UnitDelay; tperiod_CLKB_posedge : VitalDelayType := UnitDelay; -- tCLKH -- tCLKL tpw_CLKA_posedge : VitalDelayType := UnitDelay; tpw_CLKB_posedge : VitalDelayType := UnitDelay; tpw_CLKA_negedge : VitalDelayType := UnitDelay; tpw_CLKB_negedge : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tDS tsetup_A0_CLKA : VitalDelayType := UnitDelay; tsetup_B0_CLKB : VitalDelayType := UnitDelay; -- tENS tsetup_CSANeg_CLKA : VitalDelayType := UnitDelay; tsetup_WRA_CLKA : VitalDelayType := UnitDelay; tsetup_CSBNeg_CLKB : VitalDelayType := UnitDelay; tsetup_WRB_CLKB : VitalDelayType := UnitDelay; tsetup_ENA_CLKA : VitalDelayType := UnitDelay; tsetup_ENB_CLKB : VitalDelayType := UnitDelay; tsetup_MBA_CLKA : VitalDelayType := UnitDelay; tsetup_MBB_CLKB : VitalDelayType := UnitDelay; -- tRSTS tsetup_MRSNeg_CLKA : VitalDelayType := UnitDelay; tsetup_MRSNeg_CLKB : VitalDelayType := UnitDelay; tsetup_PRSNeg_CLKA : VitalDelayType := UnitDelay; tsetup_PRSNeg_CLKB : VitalDelayType := UnitDelay; -- tFSS tsetup_FS0SD_MRSNeg : VitalDelayType := UnitDelay; tsetup_FS1SEN_MRSNeg : VitalDelayType := UnitDelay; -- tBES tsetup_BEFWFT_MRSNeg : VitalDelayType := UnitDelay; -- tSPMS tsetup_SPMNeg_MRSNeg : VitalDelayType := UnitDelay; -- tSDS tsetup_FS0SD_CLKA : VitalDelayType := UnitDelay; -- tSENS tsetup_FS1SEN_CLKA : VitalDelayType := UnitDelay; -- tFWS tsetup_BEFWFT_CLKA : VitalDelayType := UnitDelay; -- thold values: hold times -- tDH thold_A0_CLKA : VitalDelayType := UnitDelay; thold_B0_CLKB : VitalDelayType := UnitDelay; -- tENH thold_CSANeg_CLKA : VitalDelayType := UnitDelay; thold_WRA_CLKA : VitalDelayType := UnitDelay; thold_CSBNeg_CLKB : VitalDelayType := UnitDelay; thold_WRB_CLKB : VitalDelayType := UnitDelay; thold_ENA_CLKA : VitalDelayType := UnitDelay; thold_ENB_CLKB : VitalDelayType := UnitDelay; thold_MBA_CLKA : VitalDelayType := UnitDelay; thold_MBB_CLKB : VitalDelayType := UnitDelay; -- tRSTH thold_MRSNeg_CLKA : VitalDelayType := UnitDelay; thold_MRSNeg_CLKB : VitalDelayType := UnitDelay; thold_PRSNeg_CLKA : VitalDelayType := UnitDelay; thold_PRSNeg_CLKB : VitalDelayType := UnitDelay; -- tFSH thold_FS0SD_MRSNeg : VitalDelayType := UnitDelay; thold_FS1SEN_MRSNeg : VitalDelayType := UnitDelay; -- tBEH thold_BEFWFT_MRSNeg : VitalDelayType := UnitDelay; -- tSPMH thold_SPMNeg_MRSNeg : VitalDelayType := UnitDelay; -- tSDH thold_FS0SD_CLKA : VitalDelayType := UnitDelay; -- tSENH thold_FS1SEN_CLKA : VitalDelayType := UnitDelay; thold_BEFWFT_CLKA : VitalDelayType := UnitDelay; -- tskew values: skew times tdevice_SKEW1 : VitalDelayType := UnitDelay; -- Skew Time, between posedge CLKA and posedge CLKB for EFNeg and FFNeg; -- between posedge CLKB and posedge CLKA for EFANeg and FFBIRB; tdevice_SKEW2 : VitalDelayType := UnitDelay; -- Skew Time, between posedge CLKA and posedge CLKB for AFBNeg and AFNeg; -- between posedge CLKB and posedge CLKA for AFNeg and AFBNeg; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; TimingModel : STRING := DefaultTimingModel ); PORT ( A0 : INOUT std_logic; ----------------------------- A1 : INOUT std_logic; -- A2 : INOUT std_logic; -- A3 : INOUT std_logic; -- A4 : INOUT std_logic; -- A5 : INOUT std_logic; -- A6 : INOUT std_logic; -- A7 : INOUT std_logic; -- A8 : INOUT std_logic; -- A9 : INOUT std_logic; -- A10 : INOUT std_logic; -- A11 : INOUT std_logic; -- A12 : INOUT std_logic; -- A13 : INOUT std_logic; -- A14 : INOUT std_logic; -- A15 : INOUT std_logic; -- A16 : INOUT std_logic; -- A17 : INOUT std_logic; -- A18 : INOUT std_logic; -- 36 pin bidirectional Port-A data bus A19 : INOUT std_logic; -- A20 : INOUT std_logic; -- A21 : INOUT std_logic; -- A22 : INOUT std_logic; -- A23 : INOUT std_logic; -- A24 : INOUT std_logic; -- A25 : INOUT std_logic; -- A26 : INOUT std_logic; -- A27 : INOUT std_logic; -- A28 : INOUT std_logic; -- A29 : INOUT std_logic; -- A30 : INOUT std_logic; -- A31 : INOUT std_logic; -- A32 : INOUT std_logic; -- A33 : INOUT std_logic; -- A34 : INOUT std_logic; -- A35 : INOUT std_logic; -------------------------------------- AENeg : OUT std_logic := 'U'; -- Almost-Empty Flag for Port-B AFNeg : OUT std_logic := 'U'; -- Almost-Full Flag for Port-A B0 : INOUT std_logic; ----------------------------- B1 : INOUT std_logic; -- B2 : INOUT std_logic; -- B3 : INOUT std_logic; -- B4 : INOUT std_logic; -- B5 : INOUT std_logic; -- B6 : INOUT std_logic; -- B7 : INOUT std_logic; -- B8 : INOUT std_logic; --⌨️ 快捷键说明
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