idt72v815.vhd

VHDL的ram和fifo model code 包含众多的厂家

    -- Empty Flag
    -- (tskew1 realization)
 
    Emp_Setint <= '1' 
        WHEN ((Write_PRint_DEL=
              to_slv(Read_Pointerint+1,AddrBitNum))
              and (Rd_RAM_Onint='1')) 
        ELSE '0';

    Sng_Emp_Resint <= '1'          -- for Single_Buffered_Empty_Flag
        WHEN ((Write_PRint_DEL=
              to_slv(Read_Pointerint+1,AddrBitNum))
              and (Write_Flint_DEL='1'))
        ELSE '0'; 
    
    for_Double_Buffered_Empty_Flag: PROCESS (RCLK)
    BEGIN
        IF RCLK'event and RCLK='1' THEN
            Dbl_Emp_Resint <=  Sng_Emp_Resint;
        END IF;
    END PROCESS;

    Emp_Resint <= --Trp_Emp_Resint WHEN FWFTint='1' ELSE
                  Dbl_Emp_Resint WHEN (Dbl_Bufint='1') or (FWFTint='1') ELSE
                  Sng_Emp_Resint ;

    Empty_Flag: PROCESS (RSNeg, RCLK)
    BEGIN
        IF RSNeg = '0' THEN
            Emptyint <= '1' ;
        ELSIF RCLK'event and RCLK='1' THEN
            IF Emp_Setint ='1' THEN        --sync set 
                Emptyint <= '1' ;
            ELSIF Emp_Resint ='1' THEN     --sync reset 
                Emptyint <= '0' ;
            END IF;
        END IF;
    END PROCESS;

    --new process
    Empty_Del_Flag: PROCESS (RSNeg, RCLK)
    BEGIN
        IF RSNeg = '0' THEN
            EmpDint <= '1' ;
        ELSIF RCLK'event and RCLK='1' THEN
                EmpDint <= Emptyint ;
        END IF;
    END PROCESS;

    EFORNeg_zd <= EmpDint WHEN FWFTint='1' -- Output_Ready
                  ELSE not Emptyint;

    ----------------------------------------------------------------------------

    WrP_mn_RdPint <= Write_Pointerint - Read_Pointerint ;

    RdP_mn_WrPint <= Read_Pointerint - Write_Pointerint;

                    -- Write_Pointer is greater that or equal to Read_Pointer
    WrP_GE_RdPint <= '1'
        WHEN  (Write_Pointerint>=Read_Pointerint) 
                --only for pre_reset simulation
        and (Write_PRint(0)/='U') and (Read_PRint(0)/='U')
        ELSE '0';

    ----------------------------------------------------------------------------
    -- PAE Flag
 
    AlmEmp_Setint <='1' WHEN
        ((WrP_GE_RdPint='1') and (WrP_mn_RdPint=to_nat(PAE_Offset_Regint)))
        or
        ((WrP_GE_RdPint='0') and
         (RdP_mn_WrPint=(RAMSize-to_nat(PAE_Offset_Regint)))
        )
        ELSE '0';

    AlmEmp_Resint <='1' WHEN
        ((WrP_GE_RdPint='1') and
         (WrP_mn_RdPint=(to_nat(PAE_Offset_Regint)+1))
        )
        or
        ((WrP_GE_RdPint='0') and
         (RdP_mn_WrPint=(RAMSize-(to_nat(PAE_Offset_Regint)+1)))
        )
        ELSE '0';

    Async_Almost_Empty_Flag: PROCESS (RSNeg, AlmEmp_Setint, AlmEmp_Resint)
    BEGIN
        IF (RSNeg='0') or (AlmEmp_Setint='1')   THEN
            Almost_Emptyint <= '1';
        ELSIF (AlmEmp_Resint='1') THEN
            Almost_Emptyint <= '0';
        END IF;
    END PROCESS;

    -- (tskew2 realization)

    Sync_Almost_Empty_Flag: PROCESS (RSNeg, RCLK)
    BEGIN
        IF RSNeg = '0' THEN
            PAE_Syncint <= '1' ;
        ELSIF RCLK'event and RCLK='1' THEN
            IF (AlmEmp_Setint_DEL='1') THEN
                PAE_Syncint <= '1' ;
            ELSIF (AlmEmp_Resint_DEL='1') THEN
                PAE_Syncint <= '0' ;
            END IF;
        END IF;
    END PROCESS;

    PAENeg_zd <= not PAE_Syncint WHEN Syncint='1' ELSE not Almost_Emptyint;

    ----------------------------------------------------------------------------
    -- Full Flag
    -- (tskew1 realization)

    Full_Setint <= '1' 
        WHEN ((to_slv(WritePnt_Sumint,AddrBitNum) =
              Read_PRint_DEL)
              and (Wr_RAM_Onint='1')) 
        ELSE '0';

                       --for_Single_Buffered_Full_Flag
    Sng_Full_Resint <= '1'
        WHEN (to_slv(WritePnt_Sumint,AddrBitNum)=
              Read_PRint_DEL)
              and (Read_Flint_DEL='1')
        ELSE '0';

    for_Double_Buffered_Full_Flag: PROCESS (WCLK)
    BEGIN
        IF WCLK'event and WCLK='1' THEN
            Dbl_Full_Resint <=  Sng_Full_Resint;
        END IF;
    END PROCESS;

    Full_Resint <= Dbl_Full_Resint WHEN ((Dbl_Bufint='1') or (FWFTint='1')) ELSE
                  Sng_Full_Resint ;

    Full_Flag: PROCESS (RSNeg, WCLK)
    BEGIN
        IF RSNeg = '0' THEN
            Fullint <= '0';
        ELSIF WCLK'event and WCLK='1' THEN
            IF  Full_Setint = '1' THEN
                Fullint <= '1' ;          --sync set 
            ELSIF Full_Resint = '1' THEN
                Fullint <= '0' ;          --sync reset
            END IF;
        END IF;
    END PROCESS;

    FFIRNeg_zd <= Fullint WHEN FWFTint='1'  -- Input_Ready
                  ELSE not Fullint;
    
    Full_Flag_Delayed_Tg: PROCESS (WCLK)
    BEGIN
        IF WCLK'event and WCLK='0' THEN
                FF_Delint <=  Fullint;
        END IF;
    END PROCESS;

    ----------------------------------------------------------------------------
    -- PAF Flag
 
    AlmFull_Setint <= '1' WHEN
        ((WrP_GE_RdPint='1') and
         (WrP_mn_RdPint=(RAMSize - to_nat(PAF_Offset_Regint)))
        )
        or
        ((WrP_GE_RdPint='0') and 
         ((RdP_mn_WrPint=to_nat(PAF_Offset_Regint))
              -- only for reset simulation
           and (PAF_Offset_Regint(0)/='U')
         )
        )
        ELSE '0';

    AlmFull_Resint <= '1' WHEN
        ((WrP_GE_RdPint='1') and
         (WrP_mn_RdPint=(RAMSize - (to_nat(PAF_Offset_Regint)+1)))
        )
        or
        ((WrP_GE_RdPint='0') and (RdP_mn_WrPint=(to_nat(PAF_Offset_Regint)+1)))
        ELSE '0';

    Async_Almost_Full_Flag: PROCESS (RSNeg, AlmFull_Resint, AlmFull_Setint)
    BEGIN
        IF (RSNeg='0') or (AlmFull_Resint='1')   THEN
            Almost_Fullint <= '0';
        ELSIF (AlmFull_Setint='1') THEN
            Almost_Fullint <= '1';
        END IF;
    END PROCESS;

    SAlmFull_Setint <= '1' WHEN
        ((WrP_GE_RdPint='1') and
         (WrP_mn_RdPint=(RAMSize - (to_nat(PAF_Offset_Regint)+1)))
        )
        or
        ((WrP_GE_RdPint='0') and 
         ((RdP_mn_WrPint=to_nat(PAF_Offset_Regint)+1)
              -- only for reset simulation
           and (PAF_Offset_Regint(0)/='U')
         )
        )
        ELSE '0';

    -- (tskew2 realization)

    AlmEmp_Setint_DEL <= AlmEmp_Setint after tdevice_SKEW2;
    AlmEmp_Resint_DEL <= AlmEmp_Resint after tdevice_SKEW2;
    SAlmFull_Setint_DEL <= SAlmFull_Setint after tdevice_SKEW2;
    AlmFull_Resint_DEL <= AlmFull_Resint after tdevice_SKEW2;

    Sync_Almost_Full_Flag: PROCESS (RSNeg, WCLK)
    BEGIN
        IF RSNeg = '0' THEN
            PAF_Syncint <= '0';
        ELSIF WCLK'event and WCLK='1' THEN
            IF  (SAlmFull_Setint_DEL='1') and
                (Wr_RAM_Onint='1')
                THEN
                PAF_Syncint <= '1' ;
            ELSIF (AlmFull_Resint_DEL='1') THEN
                PAF_Syncint <= '0' ;
            END IF;
        END IF;
    END PROCESS;

    PAFNeg_zd <= not PAF_Syncint WHEN Syncint='1' ELSE not Almost_Fullint ;

    ----------------------------------------------------------------------------
    -- Half Full Flag
 
    HlfFull_Resint <= '1' WHEN
        ((WrP_GE_RdPint='1') and (WrP_mn_RdPint = HalfSize))
        or
        ((WrP_GE_RdPint='0') and (RdP_mn_WrPint = HalfSize))
        ELSE '0';

    HlfFull_Setint <= '1' WHEN
        ((WrP_GE_RdPint='1') and (WrP_mn_RdPint = HalfSize+1))
        or
        ((WrP_GE_RdPint='0') and (RdP_mn_WrPint = HalfSize-1))
        ELSE '0';

    Half_Full_Flag: PROCESS (RSNeg, HlfFull_Resint, HlfFull_Setint)
    BEGIN
        IF (RSNeg='0') or (HlfFull_Resint='1')   THEN
            HFint <= '0';
        ELSIF (HlfFull_Setint='1') THEN
            HFint <= '1';
        END IF;
    END PROCESS;

    ----------------------------------------------------------------------------
    --  Reset Configuration Logic                                             --
    ----------------------------------------------------------------------------
    
    No_Expanint <= '1' WHEN (WXINeg='0') or (RXINeg='0') ELSE '0';

    Res_FWFTint <= '1' WHEN (WXINeg='1') and (RXINeg='0') ELSE '0';

    Res_Dbl_Bufint <= '1' WHEN (WXINeg='0') and (RXINeg='1') ELSE '0';
    
    Res_Syncint <= '1' WHEN (FLNeg='1') and ((WXINeg='0') or (RXINeg='0'))
                 ELSE '0';

    Depth_Expansion_Mode: PROCESS (RSNeg, No_Expanint)
    BEGIN
        IF RSNeg = '0' THEN
            Depth_Expanint <= not No_Expanint;
        END IF;
    END PROCESS;
    
    FWFT_Mode: PROCESS (RSNeg, Res_FWFTint)
    BEGIN
        IF RSNeg = '0' THEN
            FWFTint <= Res_FWFTint;
        END IF;
    END PROCESS;

    PAE_PAF_Sync_Mode: PROCESS (RSNeg, Res_Syncint)
    BEGIN
        IF RSNeg = '0' THEN
            Syncint <= Res_Syncint;
        END IF;
    END PROCESS;

    Double_Buffered_Mode: PROCESS (RSNeg, Res_Dbl_Bufint)
    BEGIN
        IF RSNeg = '0' THEN
            Dbl_Bufint <= Res_Dbl_Bufint;
        END IF;
    END PROCESS;

    ----------------------------------------------------------------------------
    --  Expansion Logic                                                       --
    ----------------------------------------------------------------------------

    Wr_En_Setint <= '1' WHEN
            ((RSNeg = '0') and ((No_Expanint = '1') or (FLNeg='0'))) or
            ((RSNeg = '1') and (Depth_Expanint='1') and (WXINeg='0'))
            ELSE '0';

    Wr_En_Resint <= '1' WHEN
            ((RSNeg = '0') and ((No_Expanint = '0') and (FLNeg='1')))
            ELSE '0';

    Write_Enable_Mode:
          PROCESS(Wr_En_Setint,Wr_En_Resint,WCLK)
    BEGIN
        IF (Wr_En_Setint = '1') THEN
            Write_Enableint <= '1' ;
        ELSIF (Wr_En_Resint = '1') THEN
            Write_Enableint <= '0' ;
        ELSIF WCLK'event and WCLK='1' THEN
            IF Depth_Expanint='1' THEN
                IF (Wr_RAM_Onint='1') and (Write_Pointerint=(RAMSize-1)) THEN
                    Write_Enableint <= '0';
                END IF;
            END IF;
        END IF;
    END PROCESS;

    Rd_En_Setint <= '1' WHEN
            ((RSNeg = '0') and ((No_Expanint = '1') or (FLNeg='0'))) or
            ((RSNeg = '1') and (Depth_Expanint='1') and (RXINeg='0'))
            ELSE '0';

    Rd_En_Resint <= '1' WHEN
            ((RSNeg = '0') and ((No_Expanint = '0') and (FLNeg='1')))
            ELSE '0';

    Read_Enable_Mode: 
         PROCESS (Rd_En_Resint, Rd_En_Setint, RCLK)
    BEGIN
        IF Rd_En_Setint = '1' THEN
            Read_Enableint <= '1' ;
        ELSIF Rd_En_Resint='1' THEN
            Read_Enableint <= '0' ;
        ELSIF RCLK'event and RCLK='1' THEN