idt72v815.vhd

VHDL的ram和fifo model code 包含众多的厂家

-- Wire Delays                                                                --
--------------------------------------------------------------------------------
WireDelay : BLOCK
BEGIN

    w_1:  VitalWireDelay (D0_ipd,     D0,     tipd_D0     );
    w_2:  VitalWireDelay (D1_ipd,     D1,     tipd_D1     );
    w_3:  VitalWireDelay (D2_ipd,     D2,     tipd_D2     );
    w_4:  VitalWireDelay (D3_ipd,     D3,     tipd_D3     );
    w_5:  VitalWireDelay (D4_ipd,     D4,     tipd_D4     );
    w_6:  VitalWireDelay (D5_ipd,     D5,     tipd_D5     );
    w_7:  VitalWireDelay (D6_ipd,     D6,     tipd_D6     );
    w_8:  VitalWireDelay (D7_ipd,     D7,     tipd_D7     );
    w_9:  VitalWireDelay (D8_ipd,     D8,     tipd_D8     );
    w_10: VitalWireDelay (D9_ipd,     D9,     tipd_D9     );
    w_11: VitalWireDelay (D10_ipd,    D10,    tipd_D10    );
    w_12: VitalWireDelay (D11_ipd,    D11,    tipd_D11    );
    w_13: VitalWireDelay (D12_ipd,    D12,    tipd_D12    );
    w_14: VitalWireDelay (D13_ipd,    D13,    tipd_D13    );
    w_15: VitalWireDelay (D14_ipd,    D14,    tipd_D14    );
    w_16: VitalWireDelay (D15_ipd,    D15,    tipd_D15    );
    w_17: VitalWireDelay (D16_ipd,    D16,    tipd_D16    );
    w_18: VitalWireDelay (D17_ipd,    D17,    tipd_D17    );
    w_19: VitalWireDelay (RSNeg_ipd,  RSNeg,  tipd_RSNeg  );
    w_20: VitalWireDelay (WCLK_ipd,   WCLK,   tipd_WCLK   );
    w_21: VitalWireDelay (WENNeg_ipd, WENNeg, tipd_WENNeg );
    w_22: VitalWireDelay (RCLK_ipd,   RCLK,   tipd_RCLK   );
    w_23: VitalWireDelay (RENNeg_ipd, RENNeg, tipd_RENNeg );
    w_24: VitalWireDelay (OENeg_ipd,  OENeg,  tipd_OENeg  );
    w_25: VitalWireDelay (LDNeg_ipd,  LDNeg,  tipd_LDNeg  );
    w_26: VitalWireDelay (FLNeg_ipd,  FLNeg,  tipd_FLNeg  );
    w_27: VitalWireDelay (WXINeg_ipd, WXINeg, tipd_WXINeg );
    w_28: VitalWireDelay (RXINeg_ipd, RXINeg, tipd_RXINeg );

END BLOCK;

--------------------------------------------------------------------------------
-- Main Behavior Block                                                        --
--------------------------------------------------------------------------------
VITALBehavior: BLOCK
    PORT (
        D       : IN    RAM_Word := (OTHERS => 'X');
        RSNeg   : IN    std_logic := 'X' ;
        WCLK    : IN    std_logic := 'X' ;
        WENNeg  : IN    std_logic := 'X' ;
        RCLK    : IN    std_logic := 'X' ;
        RENNeg  : IN    std_logic := 'X' ;
        OENeg   : IN    std_logic := 'X' ;
        LDNeg   : IN    std_logic := 'X' ;
        FLNeg   : IN    std_logic := 'X' ;
        WXINeg  : IN    std_logic := 'X' ;
        RXINeg  : IN    std_logic := 'X' ;
        EFORNeg   : OUT   std_logic := 'U' ;
        PAENeg  : OUT   std_logic := 'U' ;
        PAFNeg  : OUT   std_logic := 'U' ;
        FFIRNeg   : OUT   std_logic := 'U' ;
        WXOHFNeg: OUT   std_logic := 'U' ;
        RXONeg  : OUT   std_logic := 'U' ;
        Q       : OUT   RAM_Word := (OTHERS => 'U')
    );

    PORT MAP (
        D(0)     => D0_ipd,
        D(1)     => D1_ipd,
        D(2)     => D2_ipd,
        D(3)     => D3_ipd,
        D(4)     => D4_ipd,
        D(5)     => D5_ipd,
        D(6)     => D6_ipd,
        D(7)     => D7_ipd,
        D(8)     => D8_ipd,
        D(9)     => D9_ipd,
        D(10)    => D10_ipd,
        D(11)    => D11_ipd,
        D(12)    => D12_ipd,
        D(13)    => D13_ipd,
        D(14)    => D14_ipd,
        D(15)    => D15_ipd,
        D(16)    => D16_ipd,
        D(17)    => D17_ipd,
        RSNeg    => RSNeg_ipd,
        WCLK     => WCLK_ipd,
        WENNeg   => WENNeg_ipd,
        RCLK     => RCLK_ipd,
        RENNeg   => RENNeg_ipd,
        OENeg    => OENeg_ipd,
        LDNeg    => LDNeg_ipd,
        FLNeg    => FLNeg_ipd,
        WXINeg   => WXINeg_ipd,
        RXINeg   => RXINeg_ipd,
        EFORNeg    => EFORNeg,
        PAENeg   => PAENeg,
        PAFNeg   => PAFNeg,
        FFIRNeg    => FFIRNeg,
        WXOHFNeg => WXOHFNeg,
        RXONeg   => RXONeg,
        Q(0)     => Q0,
        Q(1)     => Q1,
        Q(2)     => Q2,
        Q(3)     => Q3,
        Q(4)     => Q4,
        Q(5)     => Q5,
        Q(6)     => Q6,
        Q(7)     => Q7,
        Q(8)     => Q8,
        Q(9)     => Q9,
        Q(10)    => Q10,
        Q(11)    => Q11,
        Q(12)    => Q12,
        Q(13)    => Q13,
        Q(14)    => Q14,
        Q(15)    => Q15,
        Q(16)    => Q16,
        Q(17)    => Q17
    );
        -- zero delayed outputs;
        -- actual outports are assigned in Path Delay Section

    SIGNAL  EFORNeg_zd   : std_logic ;
    SIGNAL  PAENeg_zd  : std_logic ;
    SIGNAL  PAFNeg_zd  : std_logic ;
    SIGNAL  FFIRNeg_zd   : std_logic ;
    SIGNAL  WXOHFNeg_zd: std_logic ;
    SIGNAL  RXONeg_zd  : std_logic ;
    SIGNAL  Q_zd       : RAM_Word  ;

BEGIN -- VitalBehavior block

    ----------------------------------------------------------------------------
    -- Timing Check Section                                                   --
    ----------------------------------------------------------------------------
    TimingChecks: PROCESS (D, RSNeg, WCLK, WENNeg, RCLK, RENNeg,
                           OENeg, LDNeg, WXINeg, RXINeg)

        -- Timing Check Variables

        -- Pulse Width & Period Check Variables

        VARIABLE Pviol_WCLK          : X01 := '0';
        VARIABLE PD_WCLK             : VitalPeriodDataType :=
                                       VitalPeriodDataInit;

        VARIABLE Pviol_RCLK          : X01 := '0';
        VARIABLE PD_RCLK             : VitalPeriodDataType :=
                                       VitalPeriodDataInit;

        VARIABLE Pviol_RSNeg         : X01 := '0';
        VARIABLE PD_RSNeg            : VitalPeriodDataType :=
                                       VitalPeriodDataInit;

        VARIABLE Pviol_WXINeg        : X01 := '0';
        VARIABLE PD_WXINeg           : VitalPeriodDataType :=
                                       VitalPeriodDataInit;

        VARIABLE Pviol_RXINeg        : X01 := '0';
        VARIABLE PD_RXINeg           : VitalPeriodDataType :=
                                       VitalPeriodDataInit;

       -- Setup/Hold Check Variables

        VARIABLE Tviol_D0_WCLK       : X01 := '0';
        VARIABLE TD_D0_WCLK          : VitalTimingDataType;

        VARIABLE Tviol_WENNeg_WCLK   : X01 := '0';
        VARIABLE TD_WENNeg_WCLK      : VitalTimingDataType;

        VARIABLE Tviol_RENNeg_RCLK   : X01 := '0';
        VARIABLE TD_RENNeg_RCLK      : VitalTimingDataType;

        VARIABLE Tviol_LDNeg_WCLK    : X01 := '0';
        VARIABLE TD_LDNeg_WCLK       : VitalTimingDataType;

        VARIABLE Tviol_LDNeg_RCLK    : X01 := '0';
        VARIABLE TD_LDNeg_RCLK       : VitalTimingDataType;

        VARIABLE Tviol_WENNeg_RSNeg  : X01 := '0';
        VARIABLE TD_WENNeg_RSNeg     : VitalTimingDataType;

        VARIABLE Tviol_RENNeg_RSNeg  : X01 := '0';
        VARIABLE TD_RENNeg_RSNeg     : VitalTimingDataType;

        VARIABLE Tviol_LDNeg_RSNeg   : X01 := '0';
        VARIABLE TD_LDNeg_RSNeg      : VitalTimingDataType;

        VARIABLE Tviol_WXINeg_WCLK   : X01 := '0';
        VARIABLE TD_WXINeg_WCLK      : VitalTimingDataType;

        VARIABLE Tviol_RXINeg_RCLK   : X01 := '0';
        VARIABLE TD_RXINeg_RCLK      : VitalTimingDataType;


        -- Recovery Check Variables

        VARIABLE Rviol_WENNeg_RSNeg : X01 := '0';
        VARIABLE RD_WENNeg_RSNeg    : VitalTimingDataType;

        VARIABLE Rviol_RENNeg_RSNeg : X01 := '0';
        VARIABLE RD_RENNeg_RSNeg    : VitalTimingDataType;

        VARIABLE Rviol_LDNeg_RSNeg  : X01 := '0';
        VARIABLE RD_LDNeg_RSNeg     : VitalTimingDataType;
        
        -- Skew Check Variables

        --VARIABLE Sviol_Skew1        : X01 := '0';
        --VARIABLE Sviol_Skew2        : X01 := '0';
        
        --VARIABLE WCLK_Last_Front    : time :=0 ns;
        --VARIABLE RCLK_Last_Front    : time :=0 ns;

        -- Violation variable (used to OR all individual violations)

        VARIABLE Violation           : X01 := '0';

    BEGIN  -- timing checks process

        IF  (TimingChecksOn) THEN

              Pviol_WCLK          := '0';
              Pviol_RCLK          := '0';
              Pviol_RSNeg         := '0';
              Pviol_WXINeg        := '0';
              Pviol_RXINeg        := '0';
              Tviol_D0_WCLK       := '0';
              Tviol_WENNeg_WCLK   := '0';
              Tviol_RENNeg_RCLK   := '0';
              Tviol_LDNeg_WCLK    := '0';
              Tviol_LDNeg_RCLK    := '0';
              Tviol_WENNeg_RSNeg  := '0';
              Tviol_RENNeg_RSNeg  := '0';
              Tviol_LDNeg_RSNeg   := '0';
              Tviol_WXINeg_WCLK   := '0';
              Tviol_RXINeg_RCLK   := '0';
              Rviol_WENNeg_RSNeg  := '0';
              Rviol_RENNeg_RSNeg  := '0';
              Rviol_LDNeg_RSNeg   := '0';
              
            --1 WCLK pulse (low & high) width and period check
            --  (tCLK, tCLKH, tCLKL)

            IF WCLK'event THEN 

            VitalPeriodPulseCheck (
                TestSignal      => WCLK,
                TestSignalName  => "WCLK",
                Period          => tperiod_RCLK_posedge,
                PulseWidthHigh  => tpw_RCLK_posedge,
                PulseWidthLow   => tpw_RCLK_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_WCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_WCLK);
             END IF;

            --2 RCLK pulse (low & high) width and period check
            --  (tCLK, tCLKH, tCLKL)
            IF RCLK'event THEN

            VitalPeriodPulseCheck (
                TestSignal      => RCLK,
                TestSignalName  => "RCLK",
                Period          => tperiod_RCLK_posedge,
                PulseWidthHigh  => tpw_RCLK_posedge,
                PulseWidthLow   => tpw_RCLK_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_RCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_RCLK);
            END IF;

            --3 RSNeg low pulse width check (tRS)

            IF RSNeg'event THEN
            VitalPeriodPulseCheck (
                TestSignal      => RSNeg,
                TestSignalName  => "RSNEg",
                PulseWidthLow   => tpw_RSNeg_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_RSNeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_RSNeg);
            END IF;

            --4 WXINeg low pulse width check (tXI)

            IF WXINeg'event THEN
            VitalPeriodPulseCheck (
                TestSignal      => WXINeg,
                TestSignalName  => "WXINEg",
                PulseWidthLow   => tpw_RXINeg_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_WXINeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_WXINeg);
            END IF;

            --5 RXIeg low pulse width check (tXI)

            IF RXINeg'event THEN
            VitalPeriodPulseCheck (
                TestSignal      => RXINeg,
                TestSignalName  => "RXINEg",
                PulseWidthLow   => tpw_RXINeg_negedge,
                CheckEnabled    => TRUE,
                HeaderMsg       => InstancePath & partID,
                PeriodData      => PD_RXINeg,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Pviol_RXINeg);
            END IF;

            --6 D/WCLK setup/hold time check (tDS, tDH)
            IF D'event OR (WCLK'event AND WCLK = '1') THEN

            VitalSetupHoldCheck (
                TestSignal      => D,
                TestSignalName  => "D",
                RefSignal       => WCLK,
                RefSignalName   => "WCLK",
                SetupHigh       => tsetup_D0_WCLK_noedge_posedge,
                SetupLow        => tsetup_D0_WCLK_noedge_posedge,
                HoldHigh        => thold_D0_WCLK_noedge_posedge,
                HoldLow         => thold_D0_WCLK_noedge_posedge,
                CheckEnabled    => True,
                RefTransition   => '/',
                HeaderMsg       => InstancePath & partID,
                TimingData      => TD_D0_WCLK,
                XOn             => XOn,
                MsgOn           => MsgOn,
                Violation       => Tviol_D0_WCLK);
            END IF;

            --7 WENNeg/WCLK setup/hold time check (tENS, tENH)
            IF WENNeg'event OR (WCLK'event AND WCLK = '1') THEN

            VitalSetupHoldCheck (