idt72t54242.vhd

VHDL的ram和fifo model code 包含众多的厂家

                ELSE
                    EFNeg_zd := '0';
                    FFNeg_zd := '1';
                END IF;
                Qreg := (others => '0');
                bm_Incnt :=0;
                bm_Outcnt:=0;
            END partial_reset;

            PROCEDURE count_skew
            IS
            BEGIN
                IF (tWCLKposedge - tRCLKposedge) >= tSKEW1 THEN
                minskew1RW := true;
                ELSE
                minskew1RW := false;
                END IF;

                IF (tWCLKposedge - tRCLKnegedge) >= tSKEW2 THEN
                minskew2RW := true;
                ELSE
                minskew2RW := false;
                END IF;

                IF (tWCLKposedge - tRCLKposedge) >= tSKEW3 THEN
                minskew3RW := true;
                ELSE
                minskew3RW := false;
                END IF;

                IF (tRCLKposedge - tWCLKposedge) >= tSKEW1 THEN
                minskew1WR := true;
                ELSE
                minskew1WR := false;
                END IF;

                IF (tRCLKposedge - tWCLKnegedge) >= tSKEW2 THEN
                minskew2WR := true;
                ELSE
                minskew2WR := false;
                END IF;

                IF (tRCLKposedge - tWCLKposedge) >= tSKEW3 THEN
                minskew3WR := true;
                ELSE
                minskew3WR := false;
                END IF;
            END count_skew;

            PROCEDURE write_input
            IS
            BEGIN
                IF Violation = '0' THEN
                    IF DIn(19 downto 10) /= "ZZZZZZZZZZ"  AND
                    device_mode = DUAL THEN
                        Data2 := to_nat(DIn(19 downto 10));
                    END IF;
                    IF DIn(9 downto 0) /= "ZZZZZZZZZZ" THEN
                        Data1 := to_nat(DIn(9 downto 0));
                    END IF;
                ELSE
                    Data2 := -1;
                    Data1 := -1;
                END IF;
            END write_input;

            PROCEDURE generate_output(pointer : IN Natural)
            IS
            BEGIN
                IF (RCLKIn = '1') THEN
                    time_flag_for_OE <= '1', '0' AFTER tpd_RCLK_Q0(trz0);
                    FROMRCLK := true;
                    FROMOE := false;
                END IF;
                IF memA(pointer) >= 0 THEN
                    Qreg_tmp(19 downto 10) := to_slv(memA(pointer),10);
                ELSE
                    Qreg_tmp(19 downto 10) := (OTHERS => 'X');
                END IF;
                IF memB(pointer) >= 0 THEN
                    Qreg_tmp(9 downto 0)   := to_slv(memB(pointer),10);
                ELSE
                    Qreg_tmp(9 downto 0) := (OTHERS => 'X');
                END IF;
            END generate_output;

            PROCEDURE write_register
            IS
            BEGIN

            IF rising_edge(SCLKIn) THEN
                IF device_mode = QUAD THEN
                    tmp_ser_in(118 downto 0) := tmp_ser_in(119 downto 1);
                    tmp_ser_in(119) := SIIn;
                    IF FIFOnumber = 0 THEN
                        pafoff:= to_nat(tmp_ser_in(119 downto 105));
                        paeoff:= to_nat(tmp_ser_in(104 downto 90));
                    ELSIF FIFOnumber = 1 THEN
                        pafoff:= to_nat(tmp_ser_in(89 downto 75));
                        paeoff:= to_nat(tmp_ser_in(74 downto 60));
                    ELSIF FIFOnumber = 2 THEN
                        pafoff:= to_nat(tmp_ser_in(59 downto 45));
                        paeoff:= to_nat(tmp_ser_in(44 downto 30));
                    ELSE
                        pafoff:= to_nat(tmp_ser_in(29 downto 15));
                        paeoff:= to_nat(tmp_ser_in(14 downto 0));
                    END IF;
                ELSIF device_mode = DUAL AND IWIn = '0' AND OWIn = '0' THEN
                    tmp_ser_in(58 downto 0) := tmp_ser_in(59 downto 1);
                    tmp_ser_in(59) := SIIn;
                    IF FIFOnumber = 0 THEN
                        pafoff:= to_nat(tmp_ser_in(59 downto 45));
                        paeoff:= to_nat(tmp_ser_in(44 downto 30));
                    ELSE
                        pafoff:= to_nat(tmp_ser_in(29 downto 15));
                        paeoff:= to_nat(tmp_ser_in(14 downto 0));
                    END IF;
                ELSIF (device_mode = DUAL AND (IWIn = '1' OR OWIn = '1')) THEN
                    tmp_ser_in(54 downto 0) := tmp_ser_in(55 downto 1);
                    tmp_ser_in(55) := SIIn;
                    IF FIFOnumber = 0 THEN
                        pafoff:= to_nat(tmp_ser_in(55 downto 42));
                        paeoff:= to_nat(tmp_ser_in(41 downto 28));
                    ELSE
                        pafoff:= to_nat(tmp_ser_in(27 downto 14));
                        paeoff:= to_nat(tmp_ser_in(13 downto 0));
                    END IF;
                END IF;
                IF mode_wr = DDR or mode_rd = DDR THEN
                    IF memory_model = mapped THEN
                        pafoff:=pafoff/2;
                        paeoff:=paeoff/2;
                        pafoff:=TotalLoc1-pafoff;
                    END IF;
                ELSE
                    IF memory_model = mapped THEN
                        pafoff:=TotalLoc1-pafoff;
                    ELSE
                        pafoff:=TotalLoc-pafoff;
                    END IF;
                END IF;
            END IF;

            END write_register;

            PROCEDURE read_register
            IS
            BEGIN

            IF rising_edge(SCLKIn) THEN
                IF device_mode = QUAD THEN
                    IF fs_Incnt < 120 THEN
                        SDO_zd := tmp_ser_in(fs_Incnt);
                        fs_Incnt:=fs_Incnt+1;
                    END IF;
                    IF fs_Incnt >= 119 THEN
                        fs_Incnt:=0;
                    END IF;
                ELSIF device_mode = DUAL AND IWIn = '0' AND OWIn = '0' THEN
                    IF fs_Incnt < 60 THEN
                        SDO_zd := tmp_ser_in(fs_Incnt);
                        fs_Incnt:=fs_Incnt+1;
                    END IF;
                    IF fs_Incnt >= 59 THEN
                        fs_Incnt:=0;
                    END IF;
                ELSE
                    IF fs_Incnt < 56 THEN
                        SDO_zd := tmp_ser_in(fs_Incnt);
                        fs_Incnt:=fs_Incnt+1;
                    END IF;
                    IF fs_Incnt >= 55 THEN
                        fs_Incnt:=0;
                    END IF;
                END IF;
            END IF;

            END read_register;

        BEGIN
    IF ((FIFOnumber = 0 OR FIFOnumber = 2) AND MDIn = '0') OR
            MDIn = '1' THEN
    ----------------------------------------------------------------------------
    -- Timing Check Section
    ----------------------------------------------------------------------------
    IF (TimingChecksOn) THEN

        -- tDS, tDH
        VitalSetupHoldCheck (
            TestSignal      => DIn,
            TestSignalName  => "D",
            RefSignal       => WCLKIn,
            RefSignalName   => "WCLK",
            SetupHigh       => tsetup_D0_WCLK,
            SetupLow        => tsetup_D0_WCLK,
            HoldHigh        => thold_D0_WCLK,
            HoldLow         => thold_D0_WCLK,
            CheckEnabled    => (WENNegIn='0' AND WCSNegIn='0'),
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_D_WCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_D_WCLK
        );

        VitalSetupHoldCheck (
            TestSignal      => DIn,
            TestSignalName  => "D",
            RefSignal       => WCLKIn,
            RefSignalName   => "WCLK",
            SetupHigh       => tsetup_D0_WCLK,
            SetupLow        => tsetup_D0_WCLK,
            HoldHigh        => thold_D0_WCLK,
            HoldLow         => thold_D0_WCLK,
            CheckEnabled    => (WENNegIn='0' AND WCSNegIn='0' AND mode_wr=DDR),
            RefTransition   => '\',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_D_WCLK_DDR,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_D_WCLK_DDR
        );

        -- tENS, tENH
        VitalSetupHoldCheck (
            TestSignal      => RENNegIn,
            TestSignalName  => "RENNeg",
            RefSignal       => RCLKIn,
            RefSignalName   => "RCLK",
            SetupHigh       => tsetup_RENNeg_RCLK,
            SetupLow        => tsetup_RENNeg_RCLK,
            HoldHigh        => thold_RENNeg_RCLK,
            HoldLow         => thold_RENNeg_RCLK,
            CheckEnabled    => (RCSNegIn='0' AND RENNegIn='0'),
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_RENNeg_RCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_RENNeg_RCLK
        );

        VitalSetupHoldCheck (
            TestSignal      => WENNegIn,
            TestSignalName  => "WENNeg",
            RefSignal       => WCLKIn,
            RefSignalName   => "WCLK",
            SetupHigh       => tsetup_RENNeg_RCLK,
            SetupLow        => tsetup_RENNeg_RCLK,
            HoldHigh        => thold_RENNeg_RCLK,
            HoldLow         => thold_RENNeg_RCLK,
            CheckEnabled    => (WCSNegIn='0' AND WENNegIn='0'),
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_WENNeg_WCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_WENNeg_WCLK
        );

        VitalSetupHoldCheck (
            TestSignal      => RCSNegIn,
            TestSignalName  => "RCSNeg",
            RefSignal       => RCLKIn,
            RefSignalName   => "RCLK",
            SetupHigh       => tsetup_RENNeg_RCLK,
            SetupLow        => tsetup_RENNeg_RCLK,
            HoldHigh        => thold_RENNeg_RCLK,
            HoldLow         => thold_RENNeg_RCLK,
            CheckEnabled    => (RCSNegIn='0' AND RENNegIn='0'),
            RefTransition   => '/',
            HeaderMsg       => InstancePath & PartID,
            TimingData      => TD_RCSNeg_RCLK,
            XOn             => XOn,
            MsgOn           => MsgOn,
            Violation       => Tviol_RCSNeg_RCLK
        );

        -- tSDS, tSDH
        VitalSetupHoldCheck (
            TestSignal      => SIIn,
            TestSignalName  => "SI",
            RefSignal       => SCLKIn,
            RefSignalName   => "SCLK",
            Setu