idt72t54242.vhd

VHDL的ram和fifo model code 包含众多的厂家

            VARIABLE Rviol_WENNeg_PRSNeg : X01 := '0';
            VARIABLE RD_WENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Pviol_MRSNeg        : X01 := '0';
            VARIABLE PD_MRSNeg     : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_PRSNeg        : X01 := '0';
            VARIABLE PD_PRSNeg     : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_RCLK1         : X01 := '0';
            VARIABLE PD_RCLK1      : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_RCLK2         : X01 := '0';
            VARIABLE PD_RCLK2      : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_WCLK1         : X01 := '0';
            VARIABLE PD_WCLK1      : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_WCLK2         : X01 := '0';
            VARIABLE PD_WCLK2      : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_SCLK          : X01 := '0';
            VARIABLE PD_SCLK       : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE Pviol_PDNeg         : X01 := '0';
            VARIABLE PD_PDNeg      : VitalPeriodDataType := VitalPeriodDataInit;

            VARIABLE mode_wr     : mode_type := SDR;
            VARIABLE mode_rd     : mode_type := SDR;

            VARIABLE in_mode     : match_type := SDR10;
            VARIABLE out_mode    : match_type := SDR10;

            VARIABLE wrote_in   : boolean := false;
            VARIABLE read_out   : boolean := false;

            VARIABLE device_mode : device_mode_type := QUAD;
            VARIABLE PFM_mode    : PFM_mode_type := sync;

            -- Memory array declaration
            TYPE MemStore IS ARRAY (0 to TotalLOC + 1) OF INTEGER
                             RANGE -2 TO MaxData;
                                            -- uninitialized memory -2
                                            -- unknown or corrupted memory -1
            -- Functionality Results Variables
            VARIABLE Violation    : X01 := '0';

            VARIABLE EFNeg_zd    : std_ulogic;
            VARIABLE FFNeg_zd    : std_ulogic;
            VARIABLE PAFNeg_dly  : std_ulogic;
            VARIABLE PAFNeg_zd   : std_ulogic;
            VARIABLE PAENeg_dly  : std_ulogic;
            VARIABLE PAENeg_zd   : std_ulogic;
            VARIABLE ERCLK_zd    : std_ulogic;
            VARIABLE ERENNeg_zd  : std_ulogic;
            VARIABLE Qreg   : std_logic_vector(19 downto 0) := (others => '0');
            VARIABLE Qreg_tmp: std_logic_vector(39 downto 0):=(others => '0');
            VARIABLE SDO_zd      : std_ulogic;

            VARIABLE fwft         : boolean := false;
            VARIABLE iw           : boolean := false;
            VARIABLE ow           : boolean := false;
            VARIABLE memA         : MemStore;
            VARIABLE memB         : MemStore;
            VARIABLE Data1        : Integer := 0;
            VARIABLE Data2        : Integer := 0;

            VARIABLE memory_model : memory_model_type := normal;
            VARIABLE rdptr    : natural RANGE 0 TO TotalLOC + 1
                                                            := 0; --read pointer
            VARIABLE wrptr    : natural RANGE 0 TO TotalLOC + 1
                                                            := 0;--write pointer
            VARIABLE rdptr_next : natural RANGE 0 TO TotalLOC + 1
                                                            := 0; --read pointer
            VARIABLE wrptr_next : natural RANGE 0 TO TotalLOC + 1
                                                            := 0;--write pointer
            VARIABLE paeoff   : natural RANGE 0 TO TotalLOC; --pae offset
            VARIABLE pafoff   : natural RANGE 0 TO TotalLOC; --paf offset
            VARIABLE opi      : natural RANGE 0 TO 7; --offset preset index
            VARIABLE count    : natural RANGE 0 TO TotalLOC + 1; --memory used
            VARIABLE fwftcnt  : natural RANGE 0 TO 3;  -- fwft RCLK counter
            VARIABLE fwftcnt1 : natural RANGE 0 TO 3;  -- fwft output
            VARIABLE fwftvar  : boolean := false;  -- fwft flag for outreg
            VARIABLE do_fw    : boolean := false;
            VARIABLE fw_done  : boolean := false;
            VARIABLE fwcnt    : natural := 0;

            VARIABLE opireg   : std_logic_vector(1 downto 0);
            VARIABLE outreg   : std_logic_vector(39 downto 0);
            VARIABLE outtmp   : std_logic_vector(39 downto 0);
            VARIABLE rd_upd_flg : boolean := false;
            VARIABLE wr_upd_flg : boolean := false;

            VARIABLE write_clk_paf : Natural := 0;
            VARIABLE read_clk_pae  : Natural := 0;
            VARIABLE delayed_pae : boolean := false;
            VARIABLE delayed_paf : boolean := false;

            VARIABLE Eflagcnt   : natural   := 0;
            VARIABLE PAEflagcnt : natural   := 0;
            VARIABLE PAFflagcnt : natural   := 0;
            VARIABLE Fflagcnt   : natural   := 0;

            VARIABLE TotalLoc1: natural := TotalLoc;

            VARIABLE count_rcycle : natural   := 0;
            VARIABLE count_wcycle : natural   := 0;
            VARIABLE tRCLKposedge : Time := 0 ns;
            VARIABLE tWCLKposedge : Time := 0 ns;
            VARIABLE tRCLKnegedge : Time := 0 ns;
            VARIABLE tWCLKnegedge : Time := 0 ns;
            VARIABLE tOEnegedge   : Time := 0 ns;
            VARIABLE minskew1RW   : boolean := true;
            VARIABLE minskew2RW   : boolean := true;
            VARIABLE minskew3RW   : boolean := true;
            VARIABLE minskew1WR   : boolean := true;
            VARIABLE minskew2WR   : boolean := true;
            VARIABLE minskew3WR   : boolean := true;
            VARIABLE last_done            : last_done_type := none;
            VARIABLE flag_FF              : std_logic := '0';
            VARIABLE flag_EF              : std_logic := '0';
            VARIABLE flag_PAF             : std_logic := '0';
            VARIABLE flag_PAE             : std_logic := '0';
            VARIABLE pass_EF, pass_FF, pass_PAE, pass_PAF   : boolean := false;
            VARIABLE bm_Incnt : natural RANGE 0 TO 7 := 0;
            VARIABLE bm_Outcnt: natural RANGE 0 TO 7 := 0;

            VARIABLE fs_Incnt : natural RANGE 0 to 120 := 0;
            VARIABLE tmp_ser_in     : std_logic_vector(119 downto 0) :=
                                                        (OTHERS=>'0');

            -- Output Glitch Detection Variables
            VARIABLE FFNeg_GlitchData  : VitalGlitchDataType;
            VARIABLE PAFNeg_GlitchData : VitalGlitchDataType;
            VARIABLE EFNeg_GlitchData  : VitalGlitchDataType;
            VARIABLE PAENeg_GlitchData : VitalGlitchDataType;
            VARIABLE ERCLK_GlitchData  : VitalGlitchDataType;
            VARIABLE ERENNeg_GlitchData : VitalGlitchDataType;
            VARIABLE SDO_GlitchData : VitalGlitchDataType;

            PROCEDURE master_reset
            IS
            BEGIN
                mreset <= false, true AFTER 200 ns; -- valid reset signal
                fwftcnt := 0;
                PAENeg_zd := '0';
                PAFNeg_zd := '1';
                PAENeg_dly := '0';
                PAFNeg_dly := '1';
                TotalLoc1 := TotalLoc;
                rdptr := 0;
                wrptr := 0;
                count := 0;
                fw_done := false;
                last_done := none;
                count_rcycle := 0;
                count_wcycle := 0;
                -- configuration section
                IF FWFTIn = '1' THEN
                    fwft := true;       -- fwft mode
                    EFNeg_zd := '1';
                    FFNeg_zd := '0';
                ELSE
                    fwft := false;       --idt standard mode
                    EFNeg_zd := '0';
                    FFNeg_zd := '1';
                END IF;
                IF MDIn = '0' THEN
                    device_mode := DUAL;
                ELSE
                    device_mode := QUAD;
                END IF;

                IF PFMIn = '1' THEN
                    PFM_mode := sync;
                ELSE
                    PFM_mode := async;
                END IF;
                --bus matching byte counter
                bm_Incnt :=0;
                bm_Outcnt:=0;

                IF WDDRIn = '0' THEN
                    mode_wr := SDR;
                ELSIF WDDRIn = '1' THEN
                    mode_wr := DDR;
                END IF;
                IF RDDRIn = '0' THEN
                    mode_rd := SDR;
                ELSIF RDDRIn = '1' THEN
                    mode_rd := DDR;
                END IF;

                opireg := (FSEL1In, FSEL0In);
                opi := To_Nat(opireg);
                paeoff := offsetps(opi);

                -- bus-match and rate mode - select input-output combination
                IF (device_mode = QUAD) OR
                        (device_mode = DUAL AND IWIn = '0' AND OWIn = '0') THEN
                    IF mode_wr = SDR THEN
                        in_mode := SDR10;
                    ELSE
                        in_mode := DDR10;
                    END IF;
                    IF mode_rd = SDR THEN
                        out_mode := SDR10;
                    ELSE
                        out_mode := DDR10;
                    END IF;
                ELSIF device_mode = DUAL AND IWIn = '1' AND OWIn = '0' THEN
                    IF mode_wr = SDR THEN
                        in_mode := SDR20;
                    ELSE
                        in_mode := DDR20;
                    END IF;
                    IF mode_rd = SDR THEN
                        out_mode := SDR10;
                    ELSE
                        out_mode := DDR10;
                    END IF;
                ELSIF device_mode = DUAL AND IWIn = '0' AND OWIn = '1' THEN
                    IF mode_wr = SDR THEN
                        in_mode := SDR10;
                    ELSE
                        in_mode := DDR10;
                    END IF;
                    IF mode_rd = SDR THEN
                        out_mode := SDR20;
                    ELSE
                        out_mode := DDR20;
                    END IF;
                ELSIF device_mode = DUAL AND IWIn = '1' AND OWIn = '1' THEN
                    IF mode_wr = SDR THEN
                        in_mode := SDR20;
                    ELSE
                        in_mode := DDR20;
                    END IF;
                    IF mode_rd = SDR THEN
                        out_mode := SDR20;
                    ELSE
                        out_mode := DDR20;
                    END IF;
                END IF;

                IF in_mode=SDR10 AND out_mode=SDR10 THEN
                    memory_model := normal;
                    TotalLoc1 := TotalLoc;
                ELSIF (in_mode=DDR10 AND out_mode/=DDR20) OR
                      (in_mode=SDR10 AND out_mode/=DDR20) OR
                      (in_mode/=DDR20 AND out_mode=SDR10) OR
                      (in_mode/=DDR20 AND out_mode=SDR20) OR
                    (in_mode=SDR20 AND out_mode/=DDR20) THEN
                    memory_model := mapped;
                    TotalLoc1 := TotalLoc/2;
                    paeoff := (paeoff - 1)/2;
                ELSE
                    memory_model := mapped;
                    TotalLoc1 := TotalLoc/4;
                    paeoff := (paeoff - 1)/4;
                END IF;
                pafoff := TotalLoc1 - paeoff;
                outreg := (others => '0');
                Qreg := (others => '0');
            END master_reset;

            PROCEDURE partial_reset
            IS
            BEGIN
                mreset <= false, true AFTER 200 ns; -- valid reset signal
                fwftcnt := 0;
                PAENeg_zd := '0';
                PAFNeg_zd := '1';
                PAENeg_dly := '0';
                PAFNeg_dly := '1';
                rdptr := 0;
                wrptr := 0;
                count := 0;
                fw_done := false;
                last_done := none;
                count_rcycle := 0;
                count_wcycle := 0;
                IF fwft THEN
                    EFNeg_zd := '1';
                    FFNeg_zd := '0';