idt72t54242.vhd

VHDL的ram和fifo model code 包含众多的厂家

  SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1));
  SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2));
  SKEW3: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW3, tdevice_SKEW3));

    ----------------------------------------------------------------------------
    -- Wire Delays
    ----------------------------------------------------------------------------
    WireDelay : BLOCK
    BEGIN

        w_1 : VitalWireDelay (D0_ipd, D0, tipd_D0);
        w_2 : VitalWireDelay (D1_ipd, D1, tipd_D1);
        w_3 : VitalWireDelay (D2_ipd, D2, tipd_D2);
        w_4 : VitalWireDelay (D3_ipd, D3, tipd_D3);
        w_5 : VitalWireDelay (D4_ipd, D4, tipd_D4);
        w_6 : VitalWireDelay (D5_ipd, D5, tipd_D5);
        w_7 : VitalWireDelay (D6_ipd, D6, tipd_D6);
        w_8 : VitalWireDelay (D7_ipd, D7, tipd_D7);
        w_9 : VitalWireDelay (D8_ipd, D8, tipd_D8);
        w_10 : VitalWireDelay (D9_ipd, D9, tipd_D9);
        w_11 : VitalWireDelay (D10_ipd, D10, tipd_D10);
        w_12 : VitalWireDelay (D11_ipd, D11, tipd_D11);
        w_13 : VitalWireDelay (D12_ipd, D12, tipd_D12);
        w_14 : VitalWireDelay (D13_ipd, D13, tipd_D13);
        w_15 : VitalWireDelay (D14_ipd, D14, tipd_D14);
        w_16 : VitalWireDelay (D15_ipd, D15, tipd_D15);
        w_17 : VitalWireDelay (D16_ipd, D16, tipd_D16);
        w_18 : VitalWireDelay (D17_ipd, D17, tipd_D17);
        w_19 : VitalWireDelay (D18_ipd, D18, tipd_D18);
        w_20 : VitalWireDelay (D19_ipd, D19, tipd_D19);
        w_21 : VitalWireDelay (MD_ipd, MD, tipd_MD);
        w_22 : VitalWireDelay (FSEL0_ipd, FSEL0, tipd_FSEL0);
        w_23 : VitalWireDelay (FSEL1_ipd, FSEL1, tipd_FSEL1);
        w_24 : VitalWireDelay (FWFT_ipd, FWFT, tipd_FWFT);
        w_25 : VitalWireDelay (IOSEL_ipd, IOSEL, tipd_IOSEL);
        w_26 : VitalWireDelay (IW_ipd, IW, tipd_IW);
        w_27 : VitalWireDelay (PDNeg_ipd, PDNeg, tipd_PDNeg);
        w_28 : VitalWireDelay (MRSNeg_ipd, MRSNeg, tipd_MRSNeg);
        w_29 : VitalWireDelay (OENeg_ipd, OENeg, tipd_OENeg);
        w_30 : VitalWireDelay (OW_ipd, OW, tipd_OW);
        w_31 : VitalWireDelay (PRSNeg_ipd, PRSNeg, tipd_PRSNeg);
        w_32 : VitalWireDelay (RCLK_ipd, RCLK, tipd_RCLK);
        w_33 : VitalWireDelay (RCSNeg_ipd, RCSNeg, tipd_RCSNeg);
        w_34 : VitalWireDelay (RENNeg_ipd, RENNeg, tipd_RENNeg);
        w_35 : VitalWireDelay (RDDR_ipd, RDDR, tipd_RDDR);
        w_36 : VitalWireDelay (PFM_ipd, PFM, tipd_PFM);
        w_37 : VitalWireDelay (SCLK_ipd, SCLK, tipd_SCLK);
        w_38 : VitalWireDelay (SWENNeg_ipd, SWENNeg, tipd_SWENNeg);
        w_39 : VitalWireDelay (SRENNeg_ipd, SRENNeg, tipd_SRENNeg);
        w_40 : VitalWireDelay (SI_ipd, SI, tipd_SI);
        w_41 : VitalWireDelay (WCLK_ipd, WCLK, tipd_WCLK);
        w_42 : VitalWireDelay (WCSNeg_ipd, WCSNeg, tipd_WCSNeg);
        w_43 : VitalWireDelay (WENNeg_ipd, WENNeg, tipd_WENNeg);
        w_44 : VitalWireDelay (WDDR_ipd, WDDR, tipd_WDDR);
    END BLOCK;

    ----------------------------------------------------------------------------
    -- Main Behavior Block
    ----------------------------------------------------------------------------
    Behavior: BLOCK

        PORT (
            DIn         : IN    std_logic_vector(19 DOWNTO 0);
            MDIn        : IN    std_ulogic := 'U';
            FSEL0In     : IN    std_ulogic := 'U';
            FSEL1In     : IN    std_ulogic := 'U';
            FWFTIn      : IN    std_ulogic := 'U';
            IOSELIn     : IN    std_ulogic := 'U';
            IWIn        : IN    std_ulogic := 'U';
            PDNegIn     : IN    std_ulogic := 'U';
            MRSNegIn    : IN    std_ulogic := 'U';
            OENegIn     : IN    std_ulogic := 'U';
            OWIn        : IN    std_ulogic := 'U';
            PRSNegIn    : IN    std_ulogic := 'U';
            RCLKIn      : IN    std_ulogic := 'U';
            RCSNegIn    : IN    std_ulogic := 'U';
            RENNegIn    : IN    std_ulogic := 'U';
            RDDRIn      : IN    std_ulogic := 'U';
            PFMIn       : IN    std_ulogic := 'U';
            SCLKIn      : IN    std_ulogic := 'U';
            SWENNegIn   : IN    std_ulogic := 'U';
            SRENNegIn   : IN    std_ulogic := 'U';
            SIIn        : IN    std_ulogic := 'U';
            WCLKIn      : IN    std_ulogic := 'U';
            WCSNegIn    : IN    std_ulogic := 'U';
            WENNegIn    : IN    std_ulogic := 'U';
            WDDRIn      : IN    std_ulogic := 'U';
            QOut        : OUT   std_logic_vector(19 downto 0);
            EFNegOut    : OUT   std_ulogic := 'U';
            ERCLKOut    : OUT   std_ulogic := 'U';
            ERENNegOut  : OUT   std_ulogic := 'U';
            FFNegOut    : OUT   std_ulogic := 'U';
            PAENegOut   : OUT   std_ulogic := 'U';
            PAFNegOut   : OUT   std_ulogic := 'U';
            SDOOut      : OUT   std_ulogic := 'U'
         );
        PORT MAP (
            DIn(0) => D0_ipd,
            DIn(1) => D1_ipd,
            DIn(2) => D2_ipd,
            DIn(3) => D3_ipd,
            DIn(4) => D4_ipd,
            DIn(5) => D5_ipd,
            DIn(6) => D6_ipd,
            DIn(7) => D7_ipd,
            DIn(8) => D8_ipd,
            DIn(9) => D9_ipd,
            DIn(10) => D10_ipd,
            DIn(11) => D11_ipd,
            DIn(12) => D12_ipd,
            DIn(13) => D13_ipd,
            DIn(14) => D14_ipd,
            DIn(15) => D15_ipd,
            DIn(16) => D16_ipd,
            DIn(17) => D17_ipd,
            DIn(18) => D18_ipd,
            DIn(19) => D19_ipd,
            QOut(0) => Q0,
            QOut(1) => Q1,
            QOut(2) => Q2,
            QOut(3) => Q3,
            QOut(4) => Q4,
            QOut(5) => Q5,
            QOut(6) => Q6,
            QOut(7) => Q7,
            QOut(8) => Q8,
            QOut(9) => Q9,
            QOut(10) => Q10,
            QOut(11) => Q11,
            QOut(12) => Q12,
            QOut(13) => Q13,
            QOut(14) => Q14,
            QOut(15) => Q15,
            QOut(16) => Q16,
            QOut(17) => Q17,
            QOut(18) => Q18,
            QOut(19) => Q19,
            MDIn => To_UX01(MD_ipd),
            FSEL0In => To_UX01(FSEL0_ipd),
            FSEL1In => To_UX01(FSEL1_ipd),
            FWFTIn => To_UX01(FWFT_ipd),
            IOSELIn => To_UX01(IOSEL_ipd),
            IWIn => To_UX01(IW_ipd),
            PDNegIn => To_UX01(PDNeg_ipd),
            MRSNegIn => To_UX01(MRSNeg_ipd),
            OENegIn => To_UX01(OENeg_ipd),
            OWIn => To_UX01(OW_ipd),
            PRSNegIn => To_UX01(PRSNeg_ipd),
            RCLKIn => RCLK_ipd,
            RCSNegIn => To_UX01(RCSNeg_ipd),
            RENNegIn => To_UX01(RENNeg_ipd),
            RDDRIn => To_UX01(RDDR_ipd),
            PFMIn => To_UX01(PFM_ipd),
            SCLKIn => SCLK_ipd,
            SWENNegIn => SWENNeg_ipd,
            SRENNegIn => SRENNeg_ipd,
            SIIn => SI_ipd,
            WCLKIn => WCLK_ipd,
            WCSNegIn => To_UX01(WCSNeg_ipd),
            WENNegIn => To_UX01(WENNeg_ipd),
            WDDRIn => To_UX01(WDDR_ipd),
            EFNegOut => EFNeg,
            ERCLKOut => ERCLK,
            ERENNegOut => ERENNeg,
            FFNegOut => FFNeg,
            PAENegOut => PAENeg,
            PAFNegOut => PAFNeg,
            SDOOut => SDO
        );

    SIGNAL Q_zd : std_logic_vector(19 downto 0) := (others => 'Z');
    SIGNAL mreset :  boolean := false;
    SIGNAL time_flag_for_OE : std_logic := '0';

    TYPE mode_type IS (SDR, DDR);
    TYPE match_type IS (DDR20, DDR10, SDR20, SDR10);
    TYPE offset_type IS ARRAY (0 TO 3) OF positive;
    TYPE last_done_type is (write, read, none);
    TYPE memory_model_type is (normal, mapped);
    TYPE device_mode_type is (QUAD, DUAL);
    TYPE PFM_mode_type is (async,sync);

    BEGIN
        ------------------------------------------------------------------------
        -- Behavior Process
        ------------------------------------------------------------------------
        Fifo : PROCESS (DIn, MDIn, WCLKIn, MRSNegIn, PRSNegIn, FWFTIn,
                        OWIn, FSEL0In, FSEL1In, WENNegIn, IWIn, OENegIn,
                        RENNegIn, SWENNegIn, RCLKIn, PDNegIn, RCSNegIn,
                        RDDRIn, SCLKIn, SRENNegIn, SIIn, WCSNegIn, WDDRIn)

            CONSTANT offsetps : offset_type := (7, 127, 63, 255);

            -- Timing Check Variables
            VARIABLE Tviol_D_WCLK        : X01 := '0';
            VARIABLE TD_D_WCLK           : VitalTimingDataType;

            VARIABLE Tviol_D_WCLK_DDR    : X01 := '0';
            VARIABLE TD_D_WCLK_DDR       : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_RCLK   : X01 := '0';
            VARIABLE TD_RENNeg_RCLK      : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_WCLK   : X01 := '0';
            VARIABLE TD_WENNeg_WCLK      : VitalTimingDataType;

            VARIABLE Tviol_RCSNeg_RCLK   : X01 := '0';
            VARIABLE TD_RCSNeg_RCLK      : VitalTimingDataType;

            VARIABLE Tviol_SI_SCLK       : X01 := '0';
            VARIABLE TD_SI_SCLK          : VitalTimingDataType;

            VARIABLE Tviol_SWENNeg_SCLK   : X01 := '0';
            VARIABLE TD_SWENNeg_SCLK      : VitalTimingDataType;

            VARIABLE Tviol_SRENNeg_SCLK  : X01 := '0';
            VARIABLE TD_SRENNeg_SCLK     : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_PDNeg  : X01 := '0';
            VARIABLE TD_RENNeg_PDNeg     : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_PDNeg  : X01 := '0';
            VARIABLE TD_WENNeg_PDNeg     : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_RENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_WENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_SWENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_SWENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_SRENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_SRENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_FWFT_MRSNeg   : X01 := '0';
            VARIABLE TD_FWFT_MRSNeg      : VitalTimingDataType;

            VARIABLE Tviol_FSEL1_MRSNeg  : X01 := '0';
            VARIABLE TD_FSEL1_MRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_FSEL0_MRSNeg  : X01 := '0';
            VARIABLE TD_FSEL0_MRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_MD_MRSNeg     : X01 := '0';
            VARIABLE TD_MD_MRSNeg        : VitalTimingDataType;

            VARIABLE Tviol_OW_MRSNeg     : X01 := '0';
            VARIABLE TD_OW_MRSNeg        : VitalTimingDataType;

            VARIABLE Tviol_IW_MRSNeg     : X01 := '0';
            VARIABLE TD_IW_MRSNeg        : VitalTimingDataType;

            VARIABLE Tviol_WDDR_MRSNeg   : X01 := '0';
            VARIABLE TD_WDDR_MRSNeg      : VitalTimingDataType;

            VARIABLE Tviol_RDDR_MRSNeg   : X01 := '0';
            VARIABLE TD_RDDR_MRSNeg      : VitalTimingDataType;

            VARIABLE Tviol_PFM_MRSNeg    : X01 := '0';
            VARIABLE TD_PFM_MRSNeg       : VitalTimingDataType;

            VARIABLE Tviol_IOSEL_MRSNeg  : X01 := '0';
            VARIABLE TD_IOSEL_MRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_PRSNeg : X01 := '0';
            VARIABLE TD_RENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_PRSNeg : X01 := '0';
            VARIABLE TD_WENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_SWENNeg_PRSNeg: X01 := '0';
            VARIABLE TD_SWENNeg_PRSNeg   : VitalTimingDataType;

            VARIABLE Tviol_SRENNeg_PRSNeg: X01 := '0';
            VARIABLE TD_SRENNeg_PRSNeg   : VitalTimingDataType;

            VARIABLE Rviol_RENNeg_MRSNeg : X01 := '0';
            VARIABLE RD_RENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Rviol_WENNeg_MRSNeg : X01 := '0';
            VARIABLE RD_WENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Rviol_RENNeg_PRSNeg : X01 := '0';
            VARIABLE RD_RENNeg_PRSNeg    : VitalTimingDataType;