idt72t54242.vhd

VHDL的ram和fifo model code 包含众多的厂家

--------------------------------------------------------------------------------
-- ENTITY DECLARATION
--------------------------------------------------------------------------------
ENTITY idt72t54242_onefifo IS
    GENERIC (
        -- tipd delays: interconnect path delays
        tipd_D0                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D1                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D2                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D3                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D4                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D5                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D6                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D7                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D8                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D9                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_D10                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_D11                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_D12                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_D13                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_D14                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_D15                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_D16                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_D17                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_D18                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_D19                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_MD                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_FSEL0               : VitalDelayType01 := VitalZeroDelay01;
        tipd_FSEL1               : VitalDelayType01 := VitalZeroDelay01;
        tipd_FWFT                : VitalDelayType01 := VitalZeroDelay01;
        tipd_IOSEL               : VitalDelayType01 := VitalZeroDelay01;
        tipd_IW                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_PDNeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_MRSNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_OENeg               : VitalDelayType01 := VitalZeroDelay01;
        tipd_OW                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_PRSNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_RCLK                : VitalDelayType01 := VitalZeroDelay01;
        tipd_RCSNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_RENNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_RDDR                : VitalDelayType01 := VitalZeroDelay01;
        tipd_PFM                 : VitalDelayType01 := VitalZeroDelay01;
        tipd_SCLK                : VitalDelayType01 := VitalZeroDelay01;
        tipd_SWENNeg             : VitalDelayType01 := VitalZeroDelay01;
        tipd_SRENNeg             : VitalDelayType01 := VitalZeroDelay01;
        tipd_SI                  : VitalDelayType01 := VitalZeroDelay01;
        tipd_WCLK                : VitalDelayType01 := VitalZeroDelay01;
        tipd_WCSNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_WENNeg              : VitalDelayType01 := VitalZeroDelay01;
        tipd_WDDR                : VitalDelayType01 := VitalZeroDelay01;
        -- tpd delays
        -- tA, tRCSLZ, tRCSHZ           tASO,
        tpd_RCLK_Q0              : VitalDelayType01Z := UnitDelay01Z;
        -- tOLZ, tOHZ, tOE
        tpd_OENeg_Q0             : VitalDelayType01Z := UnitDelay01Z;
        --  tPDLZ, tPDHZ
        tpd_PDNeg_Q0             : VitalDelayType01Z := UnitDelay01Z;
        -- tRSF
        tpd_MRSNeg_EFNeg         : VitalDelayType01 := UnitDelay01;
        -- tWFF
        tpd_WCLK_FFNeg           : VitalDelayType01 := UnitDelay01;
        -- tREF
        tpd_RCLK_EFNeg           : VitalDelayType01 := UnitDelay01;
        -- tPAFS
        tpd_WCLK_PAFNeg_sync     : VitalDelayType01 := UnitDelay01;
        -- tPAFA
        tpd_WCLK_PAFNeg_async    : VitalDelayType01 := UnitDelay01;
        -- tPAES
        tpd_RCLK_PAENeg_sync     : VitalDelayType01 := UnitDelay01;
        -- tPAEA
        tpd_RCLK_PAENeg_async    : VitalDelayType01 := UnitDelay01;
        -- tERCLK
        tpd_RCLK_ERCLK           : VitalDelayType01 := UnitDelay01;
        -- tCLKEN
        tpd_RCLK_ERENNeg         : VitalDelayType01 := UnitDelay01;
        -- tpw values: pulse widths
        -- tRS
        tpw_MRSNeg_negedge       : VitalDelayType   := UnitDelay;
        -- tCLKL1
        tpw_RCLK_SDR_negedge     : VitalDelayType   := UnitDelay;
        -- tCLKH1
        tpw_RCLK_SDR_posedge     : VitalDelayType   := UnitDelay;
        -- tCLKL2
        tpw_RCLK_DDR_negedge     : VitalDelayType   := UnitDelay;
        -- tCLKH2
        tpw_RCLK_DDR_posedge     : VitalDelayType   := UnitDelay;
        -- tSCKL
        tpw_SCLK_negedge         : VitalDelayType   := UnitDelay;
        -- tSCKH
        tpw_SCLK_posedge         : VitalDelayType   := UnitDelay;
        --tPDL
        tpw_PDNeg_negedge        : VitalDelayType   := UnitDelay;
        -- tCLK1
        tperiod_RCLK_SDR_posedge : VitalDelayType   := UnitDelay;
        -- tCLK2
        tperiod_RCLK_DDR_posedge : VitalDelayType   := UnitDelay;
        -- tSCLK
        tperiod_SCLK_posedge     : VitalDelayType   := UnitDelay;
        -- tsetup values: setup times
        -- tDS
        tsetup_D0_WCLK           : VitalDelayType   := UnitDelay;
        -- tENS
        tsetup_RENNeg_RCLK       : VitalDelayType   := UnitDelay;
        -- tSDS
        tsetup_SI_SCLK           : VitalDelayType   := UnitDelay;
        -- tSENS
        tsetup_SWENNeg_SCLK      : VitalDelayType   := UnitDelay;
        -- tRSS
        tsetup_RENNeg_MRSNeg     : VitalDelayType   := UnitDelay;
        -- thold values: hold times
        -- tDH
        thold_D0_WCLK            : VitalDelayType   := UnitDelay;
        -- tENH
        thold_RENNeg_RCLK        : VitalDelayType   := UnitDelay;
        -- tSDH
        thold_SI_SCLK            : VitalDelayType   := UnitDelay;
        -- tSENH
        thold_SWENNeg_SCLK       : VitalDelayType   := UnitDelay;
        --tPDH
        thold_RENNeg_PDNeg       : VitalDelayType   := UnitDelay;
        -- trecovery values: release times
        -- tRSR
        trecovery_RENNeg_MRSNeg  : VitalDelayType := UnitDelay;
        -- tSKEW1 (skew time /RCLK/WCLK(for EF/FF)
        tdevice_SKEW1  : VitalDelayType := UnitDelay;
        -- tSKEW2 (skew time /RCLK/WCLK(for EF/FF - DDR mode))
        tdevice_SKEW2  : VitalDelayType := UnitDelay;
        -- tSKEW2 (skew time /RCLK/WCLK(for PAE/PAF)
        tdevice_SKEW3  : VitalDelayType := UnitDelay;
        -- number of FIFO instance
        FIFOnumber          : NATURAL   := 1;
        -- generic control parameters
        InstancePath        : STRING    := DefaultInstancePath;
        TimingChecksOn      : BOOLEAN   := DefaultTimingChecks;
        MsgOn               : BOOLEAN   := DefaultMsgOn;
        XOn                 : BOOLEAN   := DefaultXon;
        -- For FMF SDF technology file usage
        TimingModel         : STRING    := DefaultTimingModel
    );
    PORT (
        D0              : IN    std_ulogic := 'U';
        D1              : IN    std_ulogic := 'U';
        D2              : IN    std_ulogic := 'U';
        D3              : IN    std_ulogic := 'U';
        D4              : IN    std_ulogic := 'U';
        D5              : IN    std_ulogic := 'U';
        D6              : IN    std_ulogic := 'U';
        D7              : IN    std_ulogic := 'U';
        D8              : IN    std_ulogic := 'U';
        D9              : IN    std_ulogic := 'U';
        D10             : IN    std_ulogic := 'U';
        D11             : IN    std_ulogic := 'U';
        D12             : IN    std_ulogic := 'U';
        D13             : IN    std_ulogic := 'U';
        D14             : IN    std_ulogic := 'U';
        D15             : IN    std_ulogic := 'U';
        D16             : IN    std_ulogic := 'U';
        D17             : IN    std_ulogic := 'U';
        D18             : IN    std_ulogic := 'U';
        D19             : IN    std_ulogic := 'Z';
        Q0              : OUT   std_logic := 'U';
        Q1              : OUT   std_logic := 'U';
        Q2              : OUT   std_logic := 'U';
        Q3              : OUT   std_logic := 'U';
        Q4              : OUT   std_logic := 'U';
        Q5              : OUT   std_logic := 'U';
        Q6              : OUT   std_logic := 'U';
        Q7              : OUT   std_logic := 'U';
        Q8              : OUT   std_logic := 'U';
        Q9              : OUT   std_logic := 'U';
        Q10             : OUT   std_logic := 'U';
        Q11             : OUT   std_logic := 'U';
        Q12             : OUT   std_logic := 'U';
        Q13             : OUT   std_logic := 'U';
        Q14             : OUT   std_logic := 'U';
        Q15             : OUT   std_logic := 'U';
        Q16             : OUT   std_logic := 'U';
        Q17             : OUT   std_logic := 'U';
        Q18             : OUT   std_logic := 'U';
        Q19             : OUT   std_logic := 'U';
        MD              : IN    std_ulogic := 'U';
        EFNeg           : OUT   std_ulogic := 'U';
        ERCLK           : OUT   std_ulogic := 'U';
        ERENNeg         : OUT   std_ulogic := 'U';
        FFNeg           : OUT   std_ulogic := 'U';
        FSEL0           : IN    std_ulogic := 'U';
        FSEL1           : IN    std_ulogic := 'U';
        FWFT            : IN    std_ulogic := 'U';
        IOSEL           : IN    std_ulogic := 'U';
        IW              : IN    std_ulogic := 'U';
        PDNeg           : IN    std_ulogic := 'U';
        MRSNeg          : IN    std_ulogic := 'U';
        OENeg           : IN    std_ulogic := 'U';
        OW              : IN    std_ulogic := 'U';
        PAENeg          : OUT   std_ulogic := 'U';
        PAFNeg          : OUT   std_ulogic := 'U';
        PRSNeg          : IN    std_ulogic := 'U';
        RCLK            : IN    std_ulogic := 'U';
        RCSNeg          : IN    std_ulogic := 'U';
        RENNeg          : IN    std_ulogic := 'U';
        RDDR            : IN    std_ulogic := 'U';
        PFM             : IN    std_ulogic := 'U';
        SCLK            : IN    std_ulogic := 'U';
        SWENNeg         : IN    std_ulogic := 'U';
        SRENNeg         : IN    std_ulogic := 'U';
        SI              : IN    std_ulogic := 'U';
        SDO             : OUT   std_ulogic := 'U';
        WCLK            : IN    std_ulogic := 'U';
        WCSNeg          : IN    std_ulogic := 'U';
        WENNeg          : IN    std_ulogic := 'U';
        WDDR            : IN    std_ulogic := 'U'
    );
    ATTRIBUTE VITAL_LEVEL0 of idt72t54242_onefifo : ENTITY IS TRUE;
END idt72t54242_onefifo;

--------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
--------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of idt72t54242_onefifo IS
    ATTRIBUTE VITAL_LEVEL0 of vhdl_behavioral : ARCHITECTURE IS TRUE;

    CONSTANT partID            :  String := "IDT72T54242";
    CONSTANT TotalLoc          :  POSITIVE := 32768;
    CONSTANT MaxData           :  POSITIVE := 1023;
    CONSTANT HiDbit            :  NATURAL  := 19;

    SIGNAL D0_ipd              : std_ulogic := 'U';
    SIGNAL D1_ipd              : std_ulogic := 'U';
    SIGNAL D2_ipd              : std_ulogic := 'U';
    SIGNAL D3_ipd              : std_ulogic := 'U';
    SIGNAL D4_ipd              : std_ulogic := 'U';
    SIGNAL D5_ipd              : std_ulogic := 'U';
    SIGNAL D6_ipd              : std_ulogic := 'U';
    SIGNAL D7_ipd              : std_ulogic := 'U';
    SIGNAL D8_ipd              : std_ulogic := 'U';
    SIGNAL D9_ipd              : std_ulogic := 'U';
    SIGNAL D10_ipd             : std_ulogic := 'U';
    SIGNAL D11_ipd             : std_ulogic := 'U';
    SIGNAL D12_ipd             : std_ulogic := 'U';
    SIGNAL D13_ipd             : std_ulogic := 'U';
    SIGNAL D14_ipd             : std_ulogic := 'U';
    SIGNAL D15_ipd             : std_ulogic := 'U';
    SIGNAL D16_ipd             : std_ulogic := 'U';
    SIGNAL D17_ipd             : std_ulogic := 'U';
    SIGNAL D18_ipd             : std_ulogic := 'U';
    SIGNAL D19_ipd             : std_ulogic := 'U';
    SIGNAL MD_ipd              : std_ulogic := 'U';
    SIGNAL FSEL0_ipd           : std_ulogic := 'U';
    SIGNAL FSEL1_ipd           : std_ulogic := 'U';
    SIGNAL FWFT_ipd            : std_ulogic := 'U';
    SIGNAL IOSEL_ipd           : std_ulogic := 'U';
    SIGNAL IW_ipd              : std_ulogic := 'U';
    SIGNAL PDNeg_ipd           : std_ulogic := 'U';
    SIGNAL MRSNeg_ipd          : std_ulogic := 'U';
    SIGNAL OENeg_ipd           : std_ulogic := 'U';
    SIGNAL OW_ipd              : std_ulogic := 'U';
    SIGNAL PRSNeg_ipd          : std_ulogic := 'U';
    SIGNAL RCLK_ipd            : std_ulogic := 'U';
    SIGNAL RCSNeg_ipd          : std_ulogic := 'U';
    SIGNAL RENNeg_ipd          : std_ulogic := 'U';
    SIGNAL RDDR_ipd            : std_ulogic := 'U';
    SIGNAL PFM_ipd             : std_ulogic := 'U';
    SIGNAL SCLK_ipd            : std_ulogic := 'U';
    SIGNAL SWENNeg_ipd         : std_ulogic := 'U';
    SIGNAL SRENNeg_ipd         : std_ulogic := 'U';
    SIGNAL SI_ipd              : std_ulogic := 'U';
    SIGNAL WCLK_ipd            : std_ulogic := 'U';
    SIGNAL WCSNeg_ipd          : std_ulogic := 'U';
    SIGNAL WENNeg_ipd          : std_ulogic := 'U';
    SIGNAL WDDR_ipd            : std_ulogic := 'U';
    -- SKEW stuff
    ALIAS  tSKEW1          : VitalDelayType IS tdevice_SKEW1;
    ALIAS  tSKEW2          : VitalDelayType IS tdevice_SKEW2;
    ALIAS  tSKEW3          : VitalDelayType IS tdevice_SKEW3;
    SIGNAL OpenIn, OpenOut : std_logic;

    SHARED VARIABLE FROMOE      : BOOLEAN := false;
    SHARED VARIABLE FROMRCLK    : BOOLEAN := false;
    SIGNAL FROMPD               : std_ulogic := '0';
BEGIN

--------------------------------------------------------------------------------
-- Dummy instances for exporting tSKEW vals from SDF file
-- using DEVICE construct
--------------------------------------------------------------------------------