📄 idt72t54242.vhd
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---------------------------------------------------------------------------------- File Name: idt72t54242.vhd---------------------------------------------------------------------------------- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com---- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.---- MODIFICATION HISTORY:---- version: | author: | mod date: | changes made:-- V1.0 S.Gmitrovic 05 Aug 31 Initial release------------------------------------------------------------------------------------ PART DESCRIPTION:---- Library: IDT_FIFO-- Technology: CMOS-- Part: IDT72T54242-- Description: 32,768x10x4/16,384x20x2 QUAD/DUAL TeraSync DDR/SDR FIFO--------------------------------------------------------------------------------LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL;LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL;ENTITY idt72t54242 IS GENERIC ( -- tipd delays: interconnect path delays tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; tipd_D9 : VitalDelayType01 := VitalZeroDelay01; tipd_D10 : VitalDelayType01 := VitalZeroDelay01; tipd_D11 : VitalDelayType01 := VitalZeroDelay01; tipd_D12 : VitalDelayType01 := VitalZeroDelay01; tipd_D13 : VitalDelayType01 := VitalZeroDelay01; tipd_D14 : VitalDelayType01 := VitalZeroDelay01; tipd_D15 : VitalDelayType01 := VitalZeroDelay01; tipd_D16 : VitalDelayType01 := VitalZeroDelay01; tipd_D17 : VitalDelayType01 := VitalZeroDelay01; tipd_D18 : VitalDelayType01 := VitalZeroDelay01; tipd_D19 : VitalDelayType01 := VitalZeroDelay01; tipd_D20 : VitalDelayType01 := VitalZeroDelay01; tipd_D21 : VitalDelayType01 := VitalZeroDelay01; tipd_D22 : VitalDelayType01 := VitalZeroDelay01; tipd_D23 : VitalDelayType01 := VitalZeroDelay01; tipd_D24 : VitalDelayType01 := VitalZeroDelay01; tipd_D25 : VitalDelayType01 := VitalZeroDelay01; tipd_D26 : VitalDelayType01 := VitalZeroDelay01; tipd_D27 : VitalDelayType01 := VitalZeroDelay01; tipd_D28 : VitalDelayType01 := VitalZeroDelay01; tipd_D29 : VitalDelayType01 := VitalZeroDelay01; tipd_D30 : VitalDelayType01 := VitalZeroDelay01; tipd_D31 : VitalDelayType01 := VitalZeroDelay01; tipd_D32 : VitalDelayType01 := VitalZeroDelay01; tipd_D33 : VitalDelayType01 := VitalZeroDelay01; tipd_D34 : VitalDelayType01 := VitalZeroDelay01; tipd_D35 : VitalDelayType01 := VitalZeroDelay01; tipd_D36 : VitalDelayType01 := VitalZeroDelay01; tipd_D37 : VitalDelayType01 := VitalZeroDelay01; tipd_D38 : VitalDelayType01 := VitalZeroDelay01; tipd_D39 : VitalDelayType01 := VitalZeroDelay01; tipd_MD : VitalDelayType01 := VitalZeroDelay01; tipd_FSEL0 : VitalDelayType01 := VitalZeroDelay01; tipd_FSEL1 : VitalDelayType01 := VitalZeroDelay01; tipd_FWFT : VitalDelayType01 := VitalZeroDelay01; tipd_IOSEL : VitalDelayType01 := VitalZeroDelay01; tipd_IW : VitalDelayType01 := VitalZeroDelay01; tipd_PDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_MRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OE0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_OE1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_OE2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_OE3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_OW : VitalDelayType01 := VitalZeroDelay01; tipd_PRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK0 : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK1 : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK2 : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK3 : VitalDelayType01 := VitalZeroDelay01; tipd_RCS0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_RCS1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_RCS2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_RCS3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_REN0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_REN1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_REN2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_REN3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_RDDR : VitalDelayType01 := VitalZeroDelay01; tipd_PFM : VitalDelayType01 := VitalZeroDelay01; tipd_SCLK : VitalDelayType01 := VitalZeroDelay01; tipd_SWENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SRENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_SI : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK0 : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK1 : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK2 : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK3 : VitalDelayType01 := VitalZeroDelay01; tipd_WCS0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WCS1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WCS2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WCS3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WEN0Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WEN1Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WEN2Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WEN3Neg : VitalDelayType01 := VitalZeroDelay01; tipd_WDDR : VitalDelayType01 := VitalZeroDelay01; -- generic control parameters InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXon; -- For FMF SDF technology file usage TimingModel : STRING := DefaultTimingModel ); PORT ( D0 : IN std_ulogic := 'U'; D1 : IN std_ulogic := 'U'; D2 : IN std_ulogic := 'U'; D3 : IN std_ulogic := 'U'; D4 : IN std_ulogic := 'U'; D5 : IN std_ulogic := 'U'; D6 : IN std_ulogic := 'U'; D7 : IN std_ulogic := 'U'; D8 : IN std_ulogic := 'U'; D9 : IN std_ulogic := 'U'; D10 : IN std_ulogic := 'U'; D11 : IN std_ulogic := 'U'; D12 : IN std_ulogic := 'U'; D13 : IN std_ulogic := 'U'; D14 : IN std_ulogic := 'U'; D15 : IN std_ulogic := 'U'; D16 : IN std_ulogic := 'U'; D17 : IN std_ulogic := 'U'; D18 : IN std_ulogic := 'U'; D19 : IN std_ulogic := 'U'; D20 : IN std_ulogic := 'U'; D21 : IN std_ulogic := 'U'; D22 : IN std_ulogic := 'U'; D23 : IN std_ulogic := 'U'; D24 : IN std_ulogic := 'U'; D25 : IN std_ulogic := 'U'; D26 : IN std_ulogic := 'U'; D27 : IN std_ulogic := 'U'; D28 : IN std_ulogic := 'U'; D29 : IN std_ulogic := 'U'; D30 : IN std_ulogic := 'U'; D31 : IN std_ulogic := 'U'; D32 : IN std_ulogic := 'U'; D33 : IN std_ulogic := 'U'; D34 : IN std_ulogic := 'U'; D35 : IN std_ulogic := 'U'; D36 : IN std_ulogic := 'U'; D37 : IN std_ulogic := 'U'; D38 : IN std_ulogic := 'U'; D39 : IN std_ulogic := 'U'; Q0 : OUT std_logic := 'U'; Q1 : OUT std_logic := 'U'; Q2 : OUT std_logic := 'U'; Q3 : OUT std_logic := 'U'; Q4 : OUT std_logic := 'U'; Q5 : OUT std_logic := 'U'; Q6 : OUT std_logic := 'U'; Q7 : OUT std_logic := 'U'; Q8 : OUT std_logic := 'U'; Q9 : OUT std_logic := 'U'; Q10 : OUT std_logic := 'U'; Q11 : OUT std_logic := 'U'; Q12 : OUT std_logic := 'U'; Q13 : OUT std_logic := 'U'; Q14 : OUT std_logic := 'U'; Q15 : OUT std_logic := 'U'; Q16 : OUT std_logic := 'U'; Q17 : OUT std_logic := 'U'; Q18 : OUT std_logic := 'U'; Q19 : OUT std_logic := 'U'; Q20 : OUT std_logic := 'U'; Q21 : OUT std_logic := 'U'; Q22 : OUT std_logic := 'U'; Q23 : OUT std_logic := 'U'; Q24 : OUT std_logic := 'U'; Q25 : OUT std_logic := 'U'; Q26 : OUT std_logic := 'U'; Q27 : OUT std_logic := 'U'; Q28 : OUT std_logic := 'U'; Q29 : OUT std_logic := 'U'; Q30 : OUT std_logic := 'U'; Q31 : OUT std_logic := 'U'; Q32 : OUT std_logic := 'U'; Q33 : OUT std_logic := 'U'; Q34 : OUT std_logic := 'U'; Q35 : OUT std_logic := 'U'; Q36 : OUT std_logic := 'U'; Q37 : OUT std_logic := 'U'; Q38 : OUT std_logic := 'U'; Q39 : OUT std_logic := 'U'; MD : IN std_ulogic := 'U'; EF0Neg : OUT std_ulogic := 'U'; EF1Neg : OUT std_ulogic := 'U'; EF2Neg : OUT std_ulogic := 'U'; EF3Neg : OUT std_ulogic := 'U'; ERCLK0 : OUT std_ulogic := 'U'; ERCLK1 : OUT std_ulogic := 'U'; ERCLK2 : OUT std_ulogic := 'U'; ERCLK3 : OUT std_ulogic := 'U'; EREN0Neg : OUT std_ulogic := 'U'; EREN1Neg : OUT std_ulogic := 'U'; EREN2Neg : OUT std_ulogic := 'U'; EREN3Neg : OUT std_ulogic := 'U'; FF0Neg : OUT std_ulogic := 'U'; FF1Neg : OUT std_ulogic := 'U'; FF2Neg : OUT std_ulogic := 'U'; FF3Neg : OUT std_ulogic := 'U'; FSEL0 : IN std_ulogic := 'U'; FSEL1 : IN std_ulogic := 'U'; FWFT : IN std_ulogic := 'U'; IOSEL : IN std_ulogic := 'U'; IW : IN std_ulogic := 'U'; PDNeg : IN std_ulogic := 'U'; MRSNeg : IN std_ulogic := 'U'; OE0Neg : IN std_ulogic := 'U'; OE1Neg : IN std_ulogic := 'U'; OE2Neg : IN std_ulogic := 'U'; OE3Neg : IN std_ulogic := 'U'; OW : IN std_ulogic := 'U'; PAE0Neg : OUT std_ulogic := 'U'; PAE1Neg : OUT std_ulogic := 'U'; PAE2Neg : OUT std_ulogic := 'U'; PAE3Neg : OUT std_ulogic := 'U'; PAF0Neg : OUT std_ulogic := 'U'; PAF1Neg : OUT std_ulogic := 'U'; PAF2Neg : OUT std_ulogic := 'U'; PAF3Neg : OUT std_ulogic := 'U'; PRSNeg : IN std_ulogic := 'U'; RCLK0 : IN std_ulogic := 'U'; RCLK1 : IN std_ulogic := 'U'; RCLK2 : IN std_ulogic := 'U'; RCLK3 : IN std_ulogic := 'U'; RCS0Neg : IN std_ulogic := 'U'; RCS1Neg : IN std_ulogic := 'U'; RCS2Neg : IN std_ulogic := 'U'; RCS3Neg : IN std_ulogic := 'U'; REN0Neg : IN std_ulogic := 'U'; REN1Neg : IN std_ulogic := 'U'; REN2Neg : IN std_ulogic := 'U'; REN3Neg : IN std_ulogic := 'U'; RDDR : IN std_ulogic := 'U'; PFM : IN std_ulogic := 'U'; SCLK : IN std_ulogic := 'U'; SWENNeg : IN std_ulogic := 'U'; SRENNeg : IN std_ulogic := 'U'; SI : IN std_ulogic := 'U'; SDO : OUT std_logic := 'U'; WCLK0 : IN std_ulogic := 'U'; WCLK1 : IN std_ulogic := 'U'; WCLK2 : IN std_ulogic := 'U'; WCLK3 : IN std_ulogic := 'U'; WCS0Neg : IN std_ulogic := 'U'; WCS1Neg : IN std_ulogic := 'U'; WCS2Neg : IN std_ulogic := 'U'; WCS3Neg : IN std_ulogic := 'U'; WEN0Neg : IN std_ulogic := 'U'; WEN1Neg : IN std_ulogic := 'U'; WEN2Neg : IN std_ulogic := 'U'; WEN3Neg : IN std_ulogic := 'U'; WDDR : IN std_ulogic := 'U' );ATTRIBUTE VITAL_LEVEL0 of idt72t54242 : ENTITY IS TRUE;END idt72t54242;LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.VITAL_timing.ALL; USE IEEE.VITAL_primitives.ALL;LIBRARY FMF; USE FMF.gen_utils.ALL; USE FMF.conversions.ALL;⌨️ 快捷键说明
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