idt72261.vhd

VHDL的ram和fifo model code 包含众多的厂家

        w_21: VitalWireDelay (FS_ipd    , FS    ,  tipd_FS    );

    END BLOCK WireDelay;

    ----------------------------------------------------------------------------
    -- Main Behavior Block                                                    --
    ----------------------------------------------------------------------------

    VitalBehavior: BLOCK

        PORT (
            D        : IN  std_logic_vector(FIFOWordLength-1 DOWNTO 0) :=
                                           (OTHERS => 'X');
            MRSNeg   : IN  std_ulogic := 'X';
            PRSNeg   : IN  std_ulogic := 'X';
            RTNeg    : IN  std_ulogic := 'X';
            FWFTSI   : IN  std_ulogic := 'X';
            WCLK     : IN  std_ulogic := 'X';
            WENNeg   : IN  std_ulogic := 'X';
            RCLK     : IN  std_ulogic := 'X';
            RENNeg   : IN  std_ulogic := 'X';
            OENeg    : IN  std_ulogic := 'X';
            SENNeg   : IN  std_ulogic := 'X';
            LDNeg    : IN  std_ulogic := 'X';
            FS       : IN  std_ulogic := 'X';
            FFIRNeg  : OUT std_ulogic := 'U';
            EFORNeg  : OUT std_ulogic := 'U';
            PAFNeg   : OUT std_ulogic := 'U';
            PAENeg   : OUT std_ulogic := 'U';
            HFNeg    : OUT std_ulogic := 'U';
            Q        : OUT std_ulogic_vector(FIFOWordLength -1 DOWNTO 0) :=
                                 (others => 'Z'));
        PORT MAP (
            D(0)    => D0_ipd,
            D(1)    => D1_ipd,
            D(2)    => D2_ipd,
            D(3)    => D3_ipd,
            D(4)    => D4_ipd,
            D(5)    => D5_ipd,
            D(6)    => D6_ipd,
            D(7)    => D7_ipd,
            D(8)    => D8_ipd,
            MRSNeg  => MRSNeg_ipd,
            PRSNeg  => PRSNeg_ipd,
            RTNeg   => RTNeg_ipd,
            FWFTSI  => FWFTSI_ipd,
            WCLK    => WCLK_ipd,
            WENNeg  => WENNeg_ipd,
            RCLK    => RCLK_ipd,
            RENNeg  => RENNeg_ipd,
            OENeg   => OENeg_ipd,
            SENNeg  => SENNeg_ipd,
            LDNeg   => LDNeg_ipd,
            FS      => FS_ipd,
            FFIRNeg => FFIRNeg,
            EFORNeg => EFORNeg,
            PAFNeg  => PAFNeg,
            PAENeg  => PAENeg,
            HFNeg   => HFNeg,
            Q(0)    => Q0,
            Q(1)    => Q1,
            Q(2)    => Q2,
            Q(3)    => Q3,
            Q(4)    => Q4,
            Q(5)    => Q5,
            Q(6)    => Q6,
            Q(7)    => Q7,
            Q(8)    => Q8);

-----------------------------

    SIGNAL FFIRNeg_zd : std_ulogic := 'X';
    SIGNAL EFORNeg_zd : std_ulogic := 'X';    --
    SIGNAL PAENeg_zd  : std_ulogic := 'X';    -- regs for output flags
    SIGNAL PAFNeg_zd  : std_ulogic := 'X';    --
    SIGNAL HFNeg_zd   : std_ulogic := 'X';
    SIGNAL Q_zd       : std_logic_vector(FIFOWordLength-1 DOWNTO 0);

-----------------------------

    BEGIN -- VitalBehavior block

        ------------------------------------------------------------------------
        -- Timing Check Section                                               --
        ------------------------------------------------------------------------
        TimingChecks: PROCESS (D,      MRSNeg, PRSNeg, RTNeg,  FWFTSI, WCLK,
                               WENNeg, RCLK,   RENNeg, OENeg,  SENNeg, LDNeg)

            -- Timing Check Variables

            -- Pulse Width & Period Check Variables

            VARIABLE Pviol_WCLK          : X01 := '0';
            VARIABLE PD_WCLK             : VitalPeriodDataType :=
                                           VitalPeriodDataInit;

            VARIABLE Pviol_RCLK          : X01 := '0';
            VARIABLE PD_RCLK             : VitalPeriodDataType :=
                                           VitalPeriodDataInit;

            VARIABLE Pviol_MRSNeg        : X01 := '0';
            VARIABLE PD_MRSNeg           : VitalPeriodDataType :=
                                           VitalPeriodDataInit;

            VARIABLE Pviol_PRSNeg        : X01 := '0';
            VARIABLE PD_PRSNeg           : VitalPeriodDataType :=
                                           VitalPeriodDataInit;

            -- Setup/Hold Check Variables

            VARIABLE Tviol_D0_WCLK       : X01 := '0';
            VARIABLE TD_D0_WCLK          : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_WCLK   : X01 := '0';
            VARIABLE TD_WENNeg_WCLK      : VitalTimingDataType;

            VARIABLE Tviol_SENNeg_WCLK   : X01 := '0';
            VARIABLE TD_SENNeg_WCLK      : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_RCLK   : X01 := '0';
            VARIABLE TD_RENNeg_RCLK      : VitalTimingDataType;

            VARIABLE Tviol_RTNeg_RCLK    : X01 := '0';
            VARIABLE TD_RTNeg_RCLK       : VitalTimingDataType;

            VARIABLE Tviol_LDNeg_WCLK    : X01 := '0';
            VARIABLE TD_LDNeg_WCLK       : VitalTimingDataType;

            VARIABLE Tviol_LDNeg_RCLK    : X01 := '0';
            VARIABLE TD_LDNeg_RCLK       : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_WENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_RENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_LDNeg_MRSNeg  : X01 := '0';
            VARIABLE TD_LDNeg_MRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_RTNeg_MRSNeg  : X01 := '0';
            VARIABLE TD_RTNeg_MRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_SENNeg_MRSNeg : X01 := '0';
            VARIABLE TD_SENNeg_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_PRSNeg : X01 := '0';
            VARIABLE TD_WENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_RENNeg_PRSNeg : X01 := '0';
            VARIABLE TD_RENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_RTNeg_PRSNeg  : X01 := '0';
            VARIABLE TD_RTNeg_PRSNeg     : VitalTimingDataType;

            VARIABLE Tviol_SENNeg_PRSNeg : X01 := '0';
            VARIABLE TD_SENNeg_PRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_FWFTSI_WCLK   : X01 := '0';
            VARIABLE TD_FWFTSI_WCLK      : VitalTimingDataType;

            VARIABLE Tviol_FWFTSI_MRSNeg : X01 := '0';
            VARIABLE TD_FWFTSI_MRSNeg    : VitalTimingDataType;

            VARIABLE Tviol_WENNeg_RCLK   : X01 := '0';
            VARIABLE TD_WENNeg_RCLK      : VitalTimingDataType;

            -- Violation variable (used to OR all individual violations)

            VARIABLE Violation           : X01 := '0';

        BEGIN  -- timing checks process

            IF  (TimingChecksOn) THEN

              Pviol_WCLK          := '0';
              Pviol_RCLK          := '0';
              Pviol_MRSNeg        := '0';
              Pviol_PRSNeg        := '0';
              Tviol_D0_WCLK       := '0';
              Tviol_WENNeg_WCLK   := '0';
              Tviol_SENNeg_WCLK   := '0';
              Tviol_RENNeg_RCLK   := '0';
              Tviol_RTNeg_RCLK    := '0';
              Tviol_LDNeg_WCLK    := '0';
              Tviol_LDNeg_RCLK    := '0';
              Tviol_WENNeg_MRSNeg := '0';
              Tviol_RENNeg_MRSNeg := '0';
              Tviol_LDNeg_MRSNeg  := '0';
              Tviol_RTNeg_MRSNeg  := '0';
              Tviol_SENNeg_MRSNeg := '0';
              Tviol_WENNeg_PRSNeg := '0';
              Tviol_RENNeg_PRSNeg := '0';
              Tviol_RTNeg_PRSNeg  := '0';
              Tviol_SENNeg_PRSNeg := '0';
              Tviol_FWFTSI_WCLK   := '0';
              Tviol_FWFTSI_MRSNeg := '0';
              Tviol_RENNeg_RCLK   := '0';


              --1 WCLK pulse (low & high) width and period check
              --  (tWCLK, tWCLKH, tWCLKL)

              IF WCLK'event THEN

                VitalPeriodPulseCheck (
                    TestSignal      => WCLK,
                    TestSignalName  => "WCLK",
                    Period          => tperiod_WCLK_posedge,
                    PulseWidthHigh  => tpw_WCLK_posedge,
                    PulseWidthLow   => tpw_WCLK_negedge,
                    CheckEnabled    => TRUE,
                    HeaderMsg       => InstancePath & partID,
                    PeriodData      => PD_WCLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Pviol_WCLK);

              END IF;

              --2 RCLK pulse (low & high) width and period check
              --  (tperiod_RCLK_posedge, tperiod_RCLK_posedgeH,
              --   tperiod_RCLK_posedgeL)

              IF RCLK'event THEN

                VitalPeriodPulseCheck (
                    TestSignal      => RCLK,
                    TestSignalName  => "RCLK",
                    Period          => tperiod_RCLK_posedge,
                    PulseWidthHigh  => tpw_RCLK_posedge,
                    PulseWidthLow   => tpw_RCLK_negedge,
                    CheckEnabled    => TRUE,
                    HeaderMsg       => InstancePath & partID,
                    PeriodData      => PD_RCLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Pviol_RCLK);

              END IF;

              --3 MRSNeg low pulse width check (tRS)

              IF MRSNeg'event THEN

               VitalPeriodPulseCheck (
                    TestSignal      => MRSNeg,
                    TestSignalName  => "MRSNeg",
                    PulseWidthLow   => tpw_MRSNeg_negedge,
                    CheckEnabled    => TRUE,
                    HeaderMsg       => InstancePath & partID,
                    PeriodData      => PD_MRSNeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Pviol_MRSNeg);

              END IF;

              --4 PRSNeg low pulse width check (tRS)

              IF PRSNeg'event THEN

                VitalPeriodPulseCheck (
                    TestSignal      => PRSNeg,
                    TestSignalName  => "PRSNeg",
                    PulseWidthLow   => tpw_PRSNeg_negedge,
                    CheckEnabled    => TRUE,
                    HeaderMsg       => InstancePath & partID,
                    PeriodData      => PD_PRSNeg,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Pviol_PRSNeg);

              END IF;

            IF MRSNeg /= '0' AND PRSNeg /= '0' THEN --(exclude 5-8 if reset)

              --5 D/WCLK setup/hold time check (tDS, tDH)

              IF D'event OR (WCLK'event AND WCLK = '1') THEN

                VitalSetupHoldCheck (
                    TestSignal      => D,
                    TestSignalName  => "D",
                    RefSignal       => WCLK,
                    RefSignalName   => "WCLK",
                    SetupHigh       => tsetup_D0_WCLK_noedge_posedge,
                    SetupLow        => tsetup_D0_WCLK_noedge_posedge,
                    HoldHigh        => thold_D0_WCLK_noedge_posedge,
                    HoldLow         => thold_D0_WCLK_noedge_posedge,
                    CheckEnabled    => True,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & partID,
                    TimingData      => TD_D0_WCLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_D0_WCLK);

              END IF;

              --6 WENNeg/WCLK setup/hold time check (tENS, tENH)

              IF WENNeg'event OR (WCLK'event AND WCLK = '1') THEN

                VitalSetupHoldCheck (
                    TestSignal      => WENNeg,
                    TestSignalName  => "WENNeg",
                    RefSignal       => WCLK,
                    RefSignalName   => "WCLK",
                    SetupLow        => tsetup_RENNeg_RCLK_noedge_posedge,
                    HoldHigh        => thold_RENNeg_RCLK_noedge_posedge,
                    CheckEnabled    => True,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & partID,
                    TimingData      => TD_WENNeg_WCLK,
                    XOn             => XOn,
                    MsgOn           => MsgOn,
                    Violation       => Tviol_WENNeg_WCLK);

              END IF;

              --7 SENNeg/WCLK setup/hold time check (tENS, tENH)

              IF SENNeg'event OR (WCLK'event AND WCLK = '1') THEN

                VitalSetupHoldCheck (
                    TestSignal      => SENNeg,
                    TestSignalName  => "SENNeg",
                    RefSignal       => WCLK,
                    RefSignalName   => "WCLK",
                    SetupLow        => tsetup_SENNeg_WCLK_noedge_posedge,
                    HoldHigh        => thold_SENNeg_WCLK_noedge_posedge,
                    CheckEnabled    => True,
                    RefTransition   => '/',
                    HeaderMsg       => InstancePath & partID,
                    TimingData      => TD_SENNeg_WCLK,