📄 idt72261.vhd
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---------------------------------------------------------------------------------- File name : idt72261.vhd---------------------------------------------------------------------------------- Copyright (C) 1998 Integrated Device Technology; http://www.idt.com/-- Developed by SEVA Technologies Inc. (Moscow branch) under contract to IDT-- and supported by Free Model Foundry; http://www.FreeModelFoundry.com---- This program is free software; you can redistribute it and/or modify-- it under the terms of the GNU General Public License version 2 as-- published by the Free Software Foundation.---- This VHDL model is provided on an "AS IS" basis and IDT makes absolutely no-- warranty with respect to the information contained herein. IDT DISCLAIMS-- AND CUSTOMER WAIVES ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE-- ENTIRE RISK AS TO QUALITY AND PERFORMANCE IS WITH THE USER ACCORDINGLY, IN-- NO EVENT SHALL IDT BE LIABLE FOR ANY DIRECT OR INDIRECT DAMAGES, WHETHER IN-- CONTRACT OR TORT, INCLUDING ANY LOST PROFITS OR OTHER INCIDENTAL,-- CONSEQUENTIAL, EXEMPLARY, OR PUNITIVE DAMAGES ARISING OUT OF THE USE OR-- APPLICATION OF THE VHDL model. Further, IDT reserves the right to make-- changes without notice to any product herein to improve reliability,-- function, or design. IDT does not convey any license under patent rights-- or any other intellectual property rights, including those of third parties.-- IDT is not obligated to provide maintenance or support for the licensed VHDL-- model.---- MODIFICATION HISTORY :---- version | author | mod date: | changes made-- V1.0 | Vladimir V. Erokhin | 98 MAY 10 | initial coding-- V1.1 | R. Munden | 02 MAY 19 | licensing changed to GPL------------------------------------------------------------------------------------ PART DESCRIPTION :---- Library: IDT_FIFO-- Technology: CMOS-- Part: IDT72261---- Descripton: SuperSync FIFO 32768 x 9--------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.vital_primitives.ALL; USE ieee.vital_timing.ALL;LIBRARY fmf; USE fmf.ff_package.ALL; USE fmf.gen_utils.ALL; USE fmf.conversions.to_nat; USE fmf.conversions.to_slv;---------------------------------------------------------------------------------- ENTITY DECLARATION ----------------------------------------------------------------------------------ENTITY IDT72261 IS GENERIC ( -- tipd delays: interconnect path delays -- (there must be one generic for each input pin) tipd_D0 : VitalDelayType01 := VitalZeroDelay01; tipd_D1 : VitalDelayType01 := VitalZeroDelay01; tipd_D2 : VitalDelayType01 := VitalZeroDelay01; tipd_D3 : VitalDelayType01 := VitalZeroDelay01; tipd_D4 : VitalDelayType01 := VitalZeroDelay01; tipd_D5 : VitalDelayType01 := VitalZeroDelay01; tipd_D6 : VitalDelayType01 := VitalZeroDelay01; tipd_D7 : VitalDelayType01 := VitalZeroDelay01; tipd_D8 : VitalDelayType01 := VitalZeroDelay01; tipd_MRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_PRSNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RTNeg : VitalDelayType01 := VitalZeroDelay01; tipd_FWFTSI : VitalDelayType01 := VitalZeroDelay01; tipd_WCLK : VitalDelayType01 := VitalZeroDelay01; tipd_WENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_RCLK : VitalDelayType01 := VitalZeroDelay01; tipd_RENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_OENeg : VitalDelayType01 := VitalZeroDelay01; tipd_SENNeg : VitalDelayType01 := VitalZeroDelay01; tipd_LDNeg : VitalDelayType01 := VitalZeroDelay01; tipd_FS : VitalDelayType01 := VitalZeroDelay01; -- tpd delays: propagation delays -- tRSF (applicable for all flags and Q) tpd_MRSNeg_EFORNeg : VitalDelayType01 := UnitDelay01; tpd_MRSNeg_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tA (applicable for RCLKxQ-valid tpd_RCLK_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tOLZ/tOE/tOHZ tpd_OENeg_Q0 : VitalDelayType01Z := UnitDelay01Z; -- tWFF tpd_WCLK_FFIRNeg : VitalDelayType01 := UnitDelay01; -- tREF tpd_RCLK_EFORNeg : VitalDelayType01 := UnitDelay01; -- tPAF tpd_WCLK_PAFNeg : VitalDelayType01 := UnitDelay01; -- tPAE tpd_RCLK_PAENeg : VitalDelayType01 := UnitDelay01; -- tHF (applicable for both WCLK and RCLK) tpd_RCLK_HFNeg : VitalDelayType01 := UnitDelay01; -- tpw values: pulse widths -- tperiod_RCLK_posedgeH tpw_RCLK_posedge : VitalDelayType := UnitDelay; -- tperiod_RCLK_posedgeL tpw_RCLK_negedge : VitalDelayType := UnitDelay; -- tWCLKH tpw_WCLK_posedge : VitalDelayType := UnitDelay; -- tWCLKL tpw_WCLK_negedge : VitalDelayType := UnitDelay; -- tRS (applicable for both MRS and PRS) tpw_MRSNeg_negedge : VitalDelayType := UnitDelay; tpw_PRSNeg_negedge : VitalDelayType := UnitDelay; -- tperiod values: min calculated as 1/max freq -- tperiod_RCLK_posedge tperiod_RCLK_posedge : VitalDelayType := UnitDelay; -- tWCLK tperiod_WCLK_posedge : VitalDelayType := UnitDelay; -- tsetup values: setup times -- tDS (applicable for D/WCLK) tsetup_D0_WCLK_noedge_posedge : VitalDelayType := UnitDelay; tsetup_FWFTSI_WCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tENS (applicable for both WEN/WCLK and REN/RCLK) tsetup_RTNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; tsetup_RENNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; tsetup_SENNeg_WCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tLDS (applicable for LDNeg/WCLK) tsetup_LDNeg_WCLK_noedge_posedge : VitalDelayType := UnitDelay; tsetup_LDNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tRSS (applicable for REN,WEN,LD,RT,SEN/MRS and REN,WEN,RT,SEN/PRS) tsetup_WENNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_RENNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_LDNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_RTNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_SENNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_WENNeg_PRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_RENNeg_PRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_RTNeg_PRSNeg_noedge_posedge : VitalDelayType := UnitDelay; tsetup_SENNeg_PRSNeg_noedge_posedge : VitalDelayType := UnitDelay; -- tFWFT (applicable for FWFTSI\MRSNeg tsetup_FWFTSI_MRSNeg_noedge_negedge : VitalDelayType := UnitDelay; -- tRTS tsetup_WENNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; -- thold values: hold times -- tDH (applicable for D/WCLK) thold_D0_WCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tENH (applicable for both WEN/WCLK and REN/RCLK) thold_RTNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; thold_RENNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; thold_SENNeg_WCLK_noedge_posedge : VitalDelayType := UnitDelay; -- tLDH (applicable for LDNeg/WCLK) thold_LDNeg_WCLK_noedge_posedge : VitalDelayType := UnitDelay; thold_LDNeg_RCLK_noedge_posedge : VitalDelayType := UnitDelay; -- trecovery values: recovery times -- tRSR (applicable for REN,WEN,FWFTSI,LD/MRS and REN,WEN/PRS) thold_LDNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; thold_FWFTSI_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; thold_RENNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; thold_WENNeg_MRSNeg_noedge_posedge : VitalDelayType := UnitDelay; thold_RENNeg_PRSNeg_noedge_posedge : VitalDelayType := UnitDelay; thold_WENNeg_PRSNeg_noedge_posedge : VitalDelayType := UnitDelay; -- tskew values: skew times tdevice_SKEW1 : VitalDelayType := UnitDelay; tdevice_SKEW2 : VitalDelayType := UnitDelay; InstancePath : STRING := DefaultInstancePath; TimingChecksOn : BOOLEAN := DefaultTimingChecks; MsgOn : BOOLEAN := DefaultMsgOn; XOn : BOOLEAN := DefaultXOn; TimingModel : STRING := DefaultTimingModel ); PORT ( D0 : IN std_logic := 'X'; ----------------------------- D1 : IN std_logic := 'X'; -- D2 : IN std_logic := 'X'; -- D3 : IN std_logic := 'X'; -- D4 : IN std_logic := 'X'; -- D5 : IN std_logic := 'X'; -- D6 : IN std_logic := 'X'; -- D7 : IN std_logic := 'X'; -- D8 : IN std_logic := 'X'; -- MRSNeg : IN std_logic := 'X'; -- Master Reset PRSNeg : IN std_logic := 'X'; -- Partial Reset RTNeg : IN std_logic := 'X'; -- Retransmit FWFTSI : IN std_logic := 'X'; -- First Word Fall Trough/Serial In WCLK : IN std_logic := 'X'; -- Write Clock WENNeg : IN std_logic := 'X'; -- Write Enable RCLK : IN std_logic := 'X'; -- Read Clock RENNeg : IN std_logic := 'X'; -- Read Enable OENeg : IN std_logic := 'X'; -- Output Enable SENNeg : IN std_logic := 'X'; -- Serial Enable LDNeg : IN std_logic := 'X'; -- Load FS : IN std_logic := 'X'; -- Frequency Select FFIRNeg : OUT std_logic := 'U'; -- Full Flag/Input Ready EFORNeg : OUT std_logic := 'U'; -- Empty Flag/Output Ready PAFNeg : OUT std_logic := 'U'; -- Programmable Almost Full Flag PAENeg : OUT std_logic := 'U'; -- Programmable Almost Empty Flag HFNeg : OUT std_logic := 'U'; -- Programmable Almost Empty Flag Q0 : OUT std_logic := 'U'; --------------------------------- Q1 : OUT std_logic := 'U'; -- Q2 : OUT std_logic := 'U'; -- Q3 : OUT std_logic := 'U'; -- Q4 : OUT std_logic := 'U'; -- Data Output Bus Q5 : OUT std_logic := 'U'; -- Q6 : OUT std_logic := 'U'; -- Q7 : OUT std_logic := 'U'; -- Q8 : OUT std_logic := 'U' --------------------------------- ); ATTRIBUTE vital_level0 OF IDT72261 : ENTITY IS True;END IDT72261;---------------------------------------------------------------------------------- ARCHITECTURE DECLARATION ----------------------------------------------------------------------------------ARCHITECTURE vhdl_behavioral OF IDT72261 IS ATTRIBUTE vital_level0 OF vhdl_behavioral : ARCHITECTURE IS True; CONSTANT partID : String := "IDT72261"; CONSTANT FIFOWordLength : integer := 9; -- delayed inputs (func. sec. must use these signals instead of actual inputs) SIGNAL D0_ipd : std_ulogic := 'X'; SIGNAL D1_ipd : std_ulogic := 'X'; SIGNAL D2_ipd : std_ulogic := 'X'; SIGNAL D3_ipd : std_ulogic := 'X'; SIGNAL D4_ipd : std_ulogic := 'X'; SIGNAL D5_ipd : std_ulogic := 'X'; SIGNAL D6_ipd : std_ulogic := 'X'; SIGNAL D7_ipd : std_ulogic := 'X'; SIGNAL D8_ipd : std_ulogic := 'X'; SIGNAL MRSNeg_ipd : std_ulogic := 'X'; SIGNAL PRSNeg_ipd : std_ulogic := 'X'; SIGNAL RTNeg_ipd : std_ulogic := 'X'; SIGNAL FWFTSI_ipd : std_ulogic := 'X'; SIGNAL WCLK_ipd : std_ulogic := 'X'; SIGNAL WENNeg_ipd : std_ulogic := 'X'; SIGNAL RCLK_ipd : std_ulogic := 'X'; SIGNAL RENNeg_ipd : std_ulogic := 'X'; SIGNAL OENeg_ipd : std_ulogic := 'X'; SIGNAL SENNeg_ipd : std_ulogic := 'X'; SIGNAL LDNeg_ipd : std_ulogic := 'X'; SIGNAL FS_ipd : std_ulogic := 'X'; SIGNAL D : std_ulogic_vector(FIFOWordLength-1 DOWNTO 0); SIGNAL Q : std_ulogic_vector(FIFOWordLength-1 DOWNTO 0); SIGNAL OpenIn, OpenOut : std_logic; -- Additional signals -- FIFO memory definitions (constants) -- internal signals ALIAS tpd_MRSNeg_HFNeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_MRSNeg_FFIRNeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_MRSNeg_PAFNeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_MRSNeg_PAENeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_PRSNeg_HFNeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_PRSNeg_FFIRNeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_PRSNeg_PAFNeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_PRSNeg_PAENeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_PRSNeg_EFORNeg : VitalDelayType01 IS tpd_MRSNeg_EFORNeg; ALIAS tpd_WCLK_HFNeg : VitalDelayType01 IS tpd_RCLK_HFNeg; ALIAS tpd_PRSNeg_Q0 : VitalDelayType01Z IS tpd_MRSNeg_Q0;BEGIN -- architecture body-------------------------------------------------------------------------------- -- Skew Delays-------------------------------------------------------------------------------- -- Artificient VITAL primitives wich allows pass complex non-constaint -- SKEW time into the model SKEW1: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW1, tdevice_SKEW1)); SKEW2: VitalBuf (OpenOut, OpenIn, (tdevice_SKEW2, tdevice_SKEW2)); ---------------------------------------------------------------------------- -- Wire Delays -- ---------------------------------------------------------------------------- D <= D0_ipd & D1_ipd & D2_ipd & D3_ipd & D4_ipd & D5_ipd & D6_ipd & D7_ipd & D8_ipd; WireDelay : BLOCK BEGIN w_1: VitalWireDelay (D0_ipd , D0 , tipd_D0 ); w_2: VitalWireDelay (D1_ipd , D1 , tipd_D1 ); w_3: VitalWireDelay (D2_ipd , D2 , tipd_D2 ); w_4: VitalWireDelay (D3_ipd , D3 , tipd_D3 ); w_5: VitalWireDelay (D4_ipd , D4 , tipd_D4 ); w_6: VitalWireDelay (D5_ipd , D5 , tipd_D5 ); w_7: VitalWireDelay (D6_ipd , D6 , tipd_D6 ); w_8: VitalWireDelay (D7_ipd , D7 , tipd_D7 ); w_9: VitalWireDelay (D8_ipd , D8 , tipd_D8 ); w_10: VitalWireDelay (MRSNeg_ipd, MRSNeg, tipd_MRSNeg); w_11: VitalWireDelay (PRSNeg_ipd, PRSNeg, tipd_PRSNeg); w_12: VitalWireDelay (RTNeg_ipd , RTNeg , tipd_RTNeg ); w_13: VitalWireDelay (FWFTSI_ipd, FWFTSI, tipd_FWFTSI); w_14: VitalWireDelay (WCLK_ipd , WCLK , tipd_WCLK ); w_15: VitalWireDelay (WENNeg_ipd, WENNeg, tipd_WENNeg); w_16: VitalWireDelay (RCLK_ipd , RCLK , tipd_RCLK ); w_17: VitalWireDelay (RENNeg_ipd, RENNeg, tipd_RENNeg); w_18: VitalWireDelay (OENeg_ipd , OENeg , tipd_OENeg ); w_19: VitalWireDelay (SENNeg_ipd, SENNeg, tipd_SENNeg); w_20: VitalWireDelay (LDNeg_ipd , LDNeg , tipd_LDNeg );⌨️ 快捷键说明
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