nios_0.v

和NIOS功能一样的CPU

//	The following two modules are simulation only modules used to display
//	the user friendly version of the instruction opcode

//	The instruction displayed by the following unit is the instruction
//	in the execute stage
	opcode_display_unit instruction_display (
		// inputs:
		.instruction	(ir)
	);

//	The instruction displayed by the following unit is the instruction
//	read by the instruction master. Some of the instructions read do
//	not get executed
	opcode_display_unit i_readdata_display (
		// inputs:
		.instruction	(i_readdata)
	);

endmodule
//nios_0*********************************************************************

//***************************************************************************
//	OPCode Display Unit
//
//	Module opcode_display_unit is a simulation only module used to display
//	the user friendly version of the instruction opcode
//
module opcode_display_unit (
	// inputs:
	instruction
	);

	input [15:0]	instruction;

	wire [6:0]	opcode;

	//exemplar translate_off
`ifdef MODEL_TECH
	//////////////// SIMULATION-ONLY CONTENTS
	assign opcode = ((((~instruction[15] && ~instruction[14] && ~instruction[13] && ~instruction[12] && ~instruction[11] && ~instruction[10]))))? (7'd0) :
    	(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] && ~instruction[11] &&  instruction[10]) && ~instruction[9] && ~instruction[8] && ~instruction[7]))))? (7'd1) :
		((((~instruction[15] && ~instruction[14] && ~instruction[13] && ~instruction[12] && ~instruction[11] &&  instruction[10]))))? (7'd2) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] && ~instruction[11] &&  instruction[10]) && ~instruction[9] && ~instruction[8] &&  instruction[7]))))? (7'd3) :
		((((~instruction[15] && ~instruction[14] && ~instruction[13] && ~instruction[12] &&  instruction[11] && ~instruction[10]))))? (7'd4) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] && ~instruction[11] &&  instruction[10]) &&  instruction[9] && ~instruction[8] && ~instruction[7]))))? (7'd5) :
		((((~instruction[15] && ~instruction[14] && ~instruction[13] && ~instruction[12] &&  instruction[11] &&  instruction[10]))))? (7'd6) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] && ~instruction[11] &&  instruction[10]) &&  instruction[9] && ~instruction[8] &&  instruction[7]))))? (7'd7) :
		((((~instruction[15] && ~instruction[14] && ~instruction[13] &&  instruction[12] && ~instruction[11] && ~instruction[10]))))? (7'd8) :
		((((~instruction[15] && ~instruction[14] && ~instruction[13] &&  instruction[12] && ~instruction[11] &&  instruction[10]))))? (7'd9) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] && ~instruction[10]) && ~instruction[9] && ~instruction[8]))))? (7'd10) :
		((((~instruction[15] && ~instruction[14] && ~instruction[13] &&  instruction[12] &&  instruction[11] && ~instruction[10]))))? (7'd11) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] && ~instruction[10]) && ~instruction[9] &&  instruction[8]))))? (7'd12) :
		((((~instruction[15] && ~instruction[14] && ~instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]))))? (7'd13) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] && ~instruction[10]) &&  instruction[9] && ~instruction[8]))))? (7'd14) :
		((((~instruction[15] && ~instruction[14] &&  instruction[13] && ~instruction[12] && ~instruction[11] && ~instruction[10]))))? (7'd15) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] && ~instruction[10]) &&  instruction[9] &&  instruction[8]))))? (7'd16) :
		((((~instruction[15] && ~instruction[14] &&  instruction[13] && ~instruction[12] && ~instruction[11] &&  instruction[10]))))? (7'd17) :
		((((~instruction[15] && ~instruction[14] &&  instruction[13] && ~instruction[12] &&  instruction[11] && ~instruction[10]))))? (7'd18) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) && ~instruction[9] && ~instruction[8] && ~instruction[7] && ~instruction[6] && ~instruction[5]))))? (7'd19) :
		((((~instruction[15] && ~instruction[14] &&  instruction[13] && ~instruction[12] &&  instruction[11] &&  instruction[10]))))? (7'd20) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) && ~instruction[9] && ~instruction[8] && ~instruction[7] && ~instruction[6] &&  instruction[5]))))? (7'd21) :
		((((~instruction[15] && ~instruction[14] &&  instruction[13] &&  instruction[12] && ~instruction[11] && ~instruction[10]))))? (7'd22) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) && ~instruction[9] && ~instruction[8] && ~instruction[7] &&  instruction[6] && ~instruction[5]))))? (7'd23) :
		((((~instruction[15] && ~instruction[14] &&  instruction[13] &&  instruction[12] && ~instruction[11] &&  instruction[10]))))? (7'd24) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) && ~instruction[9] && ~instruction[8] && ~instruction[7] &&  instruction[6] &&  instruction[5]))))? (7'd25) :
		((((~instruction[15] && ~instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] && ~instruction[10]))))? (7'd26) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) && ~instruction[9] && ~instruction[8] &&  instruction[7] && ~instruction[6] && ~instruction[5]))))? (7'd27) :
		((((~instruction[15] && ~instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]))))? (7'd28) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) && ~instruction[9] && ~instruction[8] &&  instruction[7] && ~instruction[6] &&  instruction[5]))))? (7'd29) :
		((((~instruction[15] &&  instruction[14] && ~instruction[13] && ~instruction[12] && ~instruction[11] && ~instruction[10]))))? (7'd30) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) && ~instruction[9] && ~instruction[8] &&  instruction[7] &&  instruction[6] && ~instruction[5]))))? (7'd31) :
		((((~instruction[15] &&  instruction[14] && ~instruction[13] && ~instruction[12] && ~instruction[11] &&  instruction[10]))))? (7'd32) :
		((((~instruction[15] &&  instruction[14] && ~instruction[13] && ~instruction[12] &&  instruction[11] && ~instruction[10]))))? (7'd33) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) && ~instruction[9] &&  instruction[8] && ~instruction[7] && ~instruction[6] && ~instruction[5]))))? (7'd34) :
		((((~instruction[15] &&  instruction[14] && ~instruction[13] && ~instruction[12] &&  instruction[11] &&  instruction[10]))))? (7'd35) :
		((((~instruction[15] &&  instruction[14] && ~instruction[13] &&  instruction[12] && ~instruction[11] && ~instruction[10]))))? (7'd36) :
		((((~instruction[15] &&  instruction[14] && ~instruction[13] &&  instruction[12] && ~instruction[11] &&  instruction[10]))))? (7'd37) :
		((((~instruction[15] &&  instruction[14] && ~instruction[13] &&  instruction[12] &&  instruction[11] && ~instruction[10]))))? (7'd38) :
		((((~instruction[15] &&  instruction[14] && ~instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]))))? (7'd39) :
		((((~instruction[15] &&  instruction[14] &&  instruction[13] && ~instruction[12] && ~instruction[11] && ~instruction[10]))))? (7'd40) :
		((((~instruction[15] &&  instruction[14] &&  instruction[13] && ~instruction[12] && ~instruction[11] &&  instruction[10]))))? (7'd41) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) && ~instruction[9] &&  instruction[8] &&  instruction[7] && ~instruction[6] &&  instruction[5]))))? (7'd42) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) && ~instruction[9] &&  instruction[8] &&  instruction[7] &&  instruction[6] && ~instruction[5]))))? (7'd43) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) &&  instruction[9] && ~instruction[8] && ~instruction[7] && ~instruction[6] && ~instruction[5]))))? (7'd44) :
		((((~instruction[15] &&  instruction[14] &&  instruction[13] && ~instruction[12] &&  instruction[11] && ~instruction[10]))))? (7'd45) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) &&  instruction[9] && ~instruction[8] && ~instruction[7] && ~instruction[6] &&  instruction[5]))))? (7'd46) :
		((((~instruction[15] &&  instruction[14] &&  instruction[13] && ~instruction[12] &&  instruction[11] &&  instruction[10]))))? (7'd47) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) &&  instruction[9] && ~instruction[8] && ~instruction[7] &&  instruction[6] && ~instruction[5]))))? (7'd48) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) &&  instruction[9] && ~instruction[8] && ~instruction[7] &&  instruction[6] &&  instruction[5]))))? (7'd49) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) &&  instruction[9] && ~instruction[8] &&  instruction[7] && ~instruction[6] && ~instruction[5]))))? (7'd50) :
		(((( instruction[15] && ~instruction[14] && ~instruction[13] && ~instruction[12] && ~instruction[11]))))? (7'd51) :
		(((( instruction[15] && ~instruction[14] && ~instruction[13] && ~instruction[12] &&  instruction[11]))))? (7'd52) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) &&  instruction[9] && ~instruction[8] &&  instruction[7] &&  instruction[6] && ~instruction[5]))))? (7'd53) :
		(((( instruction[15] && ~instruction[14] && ~instruction[13] &&  instruction[12] && ~instruction[11]))))? (7'd54) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) &&  instruction[9] && ~instruction[8] &&  instruction[7] &&  instruction[6] &&  instruction[5]))))? (7'd55) :
		(((( instruction[15] && ~instruction[14] && ~instruction[13] &&  instruction[12] &&  instruction[11]))))? (7'd56) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) &&  instruction[9] &&  instruction[8] && ~instruction[7] && ~instruction[6] && ~instruction[5]))))? (7'd57) :
		(((( instruction[15] && ~instruction[14] &&  instruction[13] && ~instruction[12]))))? (7'd58) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) &&  instruction[9] &&  instruction[8] && ~instruction[7] && ~instruction[6] &&  instruction[5]))))? (7'd59) :
		(((( instruction[15] && ~instruction[14] &&  instruction[13] &&  instruction[12]))))? (7'd60) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) &&  instruction[9] &&  instruction[8] && ~instruction[7] &&  instruction[6] && ~instruction[5]))))? (7'd61) :
		(((( instruction[15] &&  instruction[14] && ~instruction[13]))))? (7'd62) :
		(((((~instruction[15] &&  instruction[14] &&  instruction[13] &&  instruction[12] &&  instruction[11] &&  instruction[10]) &&  instruction[9] &&  instruction[8] &&  instruction[7] &&  instruction[6] && ~instruction[5]))))? (7'd63) :
		(((( instruction[15] &&  instruction[14] &&  instruction[13]))))? (7'd64) :
		(7'd65);
`endif
		//exemplar translate_on
endmodule

//***************************************************************************
//	Control Unit
//
//	Module control_unit implements the control unit which drives
//	control signals to the modules of the datapath
//
module control_unit (
	// inputs
	clk,
	ctrl_en,
	cwp_is_hi_limit,
	cwp_is_lo_limit,
	d_irq,
	d_irqnumber,
	d_wait,
	decoded_instr,
	ir,
	ld,
	next_is_ctrl_flow_instr,
	next_is_restore,
	next_is_save,
	next_is_wrctl,
	pfx,
	RA,
	reset_n,
	restore,
	save,
	skp0,
	skp1,
	skprnz,
	skprz,
	skps,
	st,
	status,
	trap,
	tret,


	// outputs
	d_read,
	d_write,
	decrement_cwp,
	disable_interrupts,
	flush_pipeline,
	flush_fifo,
	force_interrupt,
	force_read,
	force_trap_1,
	force_trap_2,
	increment_cwp,
	interrupt,
	keep_pc,
	load_nops,
	pending_interrupt,
	read_next,
	reg_write,
	save_status,
	skip
	);
	parameter READ_AND_EXECUTE=0, CHECK_PFX=1,
			  LOAD=2, STORE=3, TRAP=4,
			  STATE_X = 3'bx;

	input 			clk;
	input 			ctrl_en;
	input 			cwp_is_hi_limit;
	input 			cwp_is_lo_limit;
	input 			d_irq;
	input [5:0]		d_irqnumber;
	input 			d_wait;
	input [23:0]	decoded_instr;
	input [15:0]	ir;
	input 			ld;
	input 			next_is_ctrl_flow_instr;
	input 			next_is_restore;
	input 			next_is_save;
	input 			next_is_wrctl;
	input 			pfx;
	input [31:0]	RA;
	input 			reset_n;
	input 			restore;
	input 			save;
	input 			skp0;
	input 			skp1;
	input 			skprnz;
	input 			skprz;
	input 			skps;
	input 			st;
	input [17:0]	status;
	input 			trap;
	input 			tret;

	output 			d_read;
	output 			d_write;
	output 			decrement_cwp;
	output 			disable_interrupts;
	output 			flush_pipeline;
	output 			flush_fifo;
	output 			force_interrupt;
	output  		force_read;
	output 			force_trap_1;
	output 			force_trap_2;
	output 			increment_cwp;
	output 			interrupt;
	output 			keep_pc;
	output 			load_nops;
	output 			pending_interrupt;
	output 			read_next;
	output 			reg_write;
	output 			save_status;
	output 			skip;


	wire [3:0]	condition_code;
	wire 		handle_overflow;
	wire		handle_underflow;
	wire 		ie;
	wire [5:0]	ipri;
	wire 		is_ctrl_flow;
	wire		valid_interrupt;
	
	reg 		d_read;
	reg 		d_write;
	reg 		decrement_cwp;
	reg 		disable_interrupts;
	reg 		flush_fifo;
	reg 		force_interrupt;
	reg 		force_trap_1;
	reg 		force_trap_2;
	reg 		increment_cwp;
	reg 		interrupt;
	reg 		interrupt_reg;
	reg [2:0]	next_state;
	reg 		old_force_read;
	reg 		old_old_force_read;
	reg 		read_next;
	reg 		reg_write;
	reg [2:0]	state;
	reg 		skip_condition;
	reg 		skip;


	// Condition code for the SKPS instruction is encoded in IMM4w
	assign condition_code = ir[3:0];
	// If the interrupt is going to be accepted, flush the pipeline
	assign flush_pipeline = pending_interrupt |
							// Do the same for the TRAP
							// next_state == TRAP insures that we don't do that twice for the interrupt
							(disable_interrupts == 1 && next_state == TRAP) |
							// Do the same when overflow/underflow happens
							force_read;
	// When the interrupt is pushed into the pipeline, the instruction register is forced to read
	// the appropriate TRAP instruction
	assign force_read = force_interrupt | force_trap_1 | force_trap_2;
	// Underflows can be handled if the interrupts are enabled, and IPRI is greater than 1
	assign handle_underflow = (ie == 1) && (ipri > 6'd1);
	// Overflows can be handled if the interrupts are enabled, and IPRI is greater than 2
	assign handle_overflow = (ie == 1) && (ipri > 6'd2);
	// Interrupt enable bit is bit 15 of the status register
	assign ie = status [15];
	// IPRI is also part of the status register
	assign ipri = status [14:9];
	// Control-flow instructions are detected using 3 bits of the decoded instruction
	// (see instruction decoder signals for further explanation)
	assign is_ctrl_flow = decoded_instr [14] & ~decoded_instr [13] & ~decoded_instr [12];
	// When the TRAP is being pushed into the pipeline, the PC value needs to be preserved until the
	// TRAP instruction reaches the execute stage and saves it (as a return address)
	assign keep_pc = force_read | old_force_read | old_old_force_read | pending_interrupt;
	// At the same time, NOPs need to be pushed into the pipeline after the TRAP instruction
	// This is the easiest way to set all other signals properly
	assign load_nops = keep_pc;
	// Interrupts are only accepted in READ_AND_EXECUTE state
	// Therefore, pending_interrupt signal is set when the interrupt is about to be accepted
	assign pending_interrupt = (valid_interrupt == 1 && next_state == READ_AND_EXECUTE);
	// Status needs to be saved always when disable_interrupt is issued, except when a TRAP
	// instruction in the program is the cause of the interrupt, because the status
	// has already been saved and changed, so saving it once more
	// overwrites the value that has been saved
	assign save_status = disable_interrupts & ~interrupt;
	// Interrupt is valid only if d_irq signal is high, interrupts are enabled,
	// d_irqnumber is lower than the current ipri, the previous instruction was not PFX,
	// we are not in delay slot, the instruction is not the control-flow instruction,
	// SAVE, RESTORE or WRCTL, and we are not already handling an interrupt.
	// Notice that this signal is registered before it is tested by the FSM, so next_is signals
	// actually refer to the instructions that will be in the execute stage when the interrupt is handled
	// Some of these conditions could be relaxed if the fast interrupt handling is very important
	// by adding guard conditions elsewhere
	assign valid_interrupt = (d_irq == 1) && (ie == 1) && (d_irqnumber < ipri) && (pfx == 0)
								&& (is_ctrl_flow == 0) && (next_is_ctrl_flow_instr == 0)
								&& (disable_interrupts == 0) && (next_is_save == 0)
								&& (next_is_restore == 0) && (next_is_wrctl == 0);

	// Signal interrupt is set when the pushed TRAP instruction is in the execute stage
	// (old_old_force_read is set). It will remain set only for one cycle since
	// old_old_force_read is set for one cycle only, and the TRAP reaches the execute stage
	// in the same cycle
	always @(negedge reset_n or posedge clk)
	begin
		if (reset_n == 0) interrupt <= 0;
		else if (old_old_force_read | (~old_old_force_read & trap)) interrupt <= old_old_force_read;
	end

	// interrupt_reg registers the valid_interrupt signal, so it can be used by the FSM
	// Registering the signal removes possible critical path
	always @(negedge reset_n or posedge clk)
	begin
		if (reset_n == 0) interrupt_reg <= 0;
		else interrupt_reg <= valid_interrupt;
	end

	// old_force_read delays the signal force_read for one cycle
	always @(negedge reset_n or posedge clk)
	begin
		if (reset_n == 0) old_force_read <= 0;
		else old_force_read <= force_read;
	end

	// old_old_force_read delays the signal old_force_read for one cycle
	// (or signal force_read for two cycles)
	always @(negedge reset_n or posedge clk)
	begin
		if (reset_n == 0) old_old_force_read <= 0;
		else old_old_force_read <= old_force_read;
	end

	// Skip condition is signal used by FSM when SKPS instruction is handled
	// The condition is set according to the condition code encoded in the IMM4w
	// field in the SKPS instruction 
	always @ (status or condition_code)
	begin
		case (condition_code)
		4'b0000: skip_condition = status [0];	//C
		4'b0001: skip_condition = ~status [0];	//~C
		4'b0010: skip_condition = status [1];	//Z
		4'b0011: skip_condition = ~status [1];	//~Z
		4'b0100: skip_condition = status [3];	//N
		4'b0101: skip_condition = ~status [3];	//~N
		4'b0110: skip_condition = ~(status [3] ^ status [2]);	//~(N xor V)
		4'b0111: skip_condition = status [3] ^ status [2];		//N xor V
		4'b1000: skip_condition = status[1] | (status [3] ^ status [2]);	//Z or (N xor V)
		4'b1001: skip_condition = ~(status[1] | (status [3] ^ status [2]));	//~(Z or (N xor V))