nios_0.v

和NIOS功能一样的CPU

/***************************************************************************
    UT Nios Soft-Core Processor v1.00
    Copyright (C) by Franjo Plavec 2004

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License Version 2, as
    published by the Free Software Foundation.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

    The full text of the GNU General Public License is given at the end of
    this file.
*****************************************************************************/
	
/******************************Usage instructions*****************************
	To use UT Nios, the Nios Embedded Processor from Altera
	has to be installed on your system, since the bus, memory
	and peripheral logic is necessary to build a useful system.

	UT Nios can be used in a system in place of Altera Nios.
	When configuring Altera Nios, make sure that cache support is
	disabled, and that the "Multiplier" option in Hardware tab of
	the Nios configuration page in SOPC Builder is set to "Software".
	This ensures that the libraries generated by the SOPC Builder
	do not use caches and hardware multiplication, which are not
	currently supported by UT Nios.

	UT Nios has several customizable parameters, of which at least two
	have to be customized for the processor to function properly.
	The two options are START_ADDRESS and VECTOR_TABLE_ADDRESS.
	  START_ADDRESS defines the starting address of the program.
	The value of this parameter should be equal to the "Address" of
	the "Reset Location" in "More Settings" tab of the SOPC Builder
	  VECTOR_TABLE_ADDRESS - memory address of the interrupt vector table.
	The value of this parameter should be equal to the "Address" of the
	"Vector Table" in "More Settings" tab of the SOPC Builder.
	See the `define statements below to set the options.
	
	To use UT Nios instead of Altera Nios, simply replace the nios_0.v
	file in the project folder generated by the SOPC Builder with this file
	file provided (Notice that "nios_0" is a default name for the first
	processor in the system. If you change the processor name manually,
	the file name will correspond to the name given to the processor.
	In such case, this file should be renamed to the given name,
	and the top level module nios_0 should also be given the same name.)
	If the instruction decoder is implemented in memory (default), two
	mif (Memory Initialization File) files (instr_mem_one.mif and
	instr_mem_two.mif) should be copied to the project folder.

	To simulate the system behaviour using ModelSim, the files instr_mem_one.dat
	and instr_mem_two.dat have to be copied to the simulation folder (along
	with all of the changes described above).
	The simulation folder is usually named <system name>_sim, where the
	<system name> is the name of the Nios based system, as specified on the
	page 2a of the MegaWizard Plug-In Manager when instantiating the system.

	Files instr_mem_one.hex and instr_mem_two.hex are not used in 
	a Quartus based design flow, and are provided for compatibility
	with other tools.

	
	This file comes AS IS, WITHOUT ANY GUARANTEED SUPPORT!
	For more information on UT Nios, refer to the master's thesis:
	F. Plavec: Soft-Core Processor Design, which can be downloaded from:
	http://www.eecg.toronto.edu/~plavec/utnios.html

	Comments and bug reports are welcome, and should be sent to:
	[e-mail], with subject line "UT Nios Comment/Bug Report"

	Bug report should ideally be accompanied with the Quartus project which
	exhibits the problem, along with the source code of the program running
	on the system, and a detailed description of the problem.
	Before filing a bug report, please make sure that the cause of the
	problem is UT Nios. The easiest way to verify this is to use the
	Altera Nios in the same	system configuration, and make sure that the
	problem	disappears. If the problem remains, the problem is likely in
	the bus or peripheral logic.
*****************************************************************************/


//***************************************************************************
// The following `define statements can be modified to customize
// the processor paramaters
// The parameter values should correspond to the values set in the
// SOPC Builder. Parameter meanings are as follows:
//	FIFO_SIZE - the size of the fifo buffer in the processor prefetch unit.
//	            This parameter is specific to UT Nios, and should be set to
//	            the latency of the slowest instruction memory in the system
//	            (the instruction memory with the highest latency) for maximum
//	            performance.
//	LOG_REGISTER_FILE_SIZE - base 10 logarithm of the number of registers
//	                         in the register file (6, 7, and 8 for 128, 256,
//	                         and 512 registers, respectively). This parameter
//	                         should be set according to the register file
//	                         size specified in the Hardware tab of the Nios
//	                         processor configuration options
//	START_ADDRESS - starting address of the program. The value of this
//	                parameter should be equal to the Address of the Reset
//	                Location in "More Settings" tab of the SOPC Builder
//	VECTOR_TABLE_ADDRESS - memory address of the interrupt vector table.
//	                       The value of this parameter should be equal to the
//	                       Address of the Vector Table in "More Settings" tab
//	                       of the SOPC Builder
//***************************************************************************
`define FIFO_SIZE 2
`define LOG_REGISTER_FILE_SIZE 9
`define START_ADDRESS 32'h104000
`define VECTOR_TABLE_ADDRESS 32'h7f00
//***************************************************************************
// The following `define statement declares that the instruction decoder
// should be implemented in on-chip memory. Comment it to implement
// the decoder in logic.
//***************************************************************************
`define DECODER_IN_MEMORY
//***************************************************************************
// The following `define statement declares that one of the data memories has
// zero latency. None of the memory modules at this time have zero latency,
// so this should be commented. If custom memory modules with zero latency
// are added to the system, uncommenting the statement may improve performance
//***************************************************************************
//`define ZERO_LATENCY
//***************************************************************************
// Naming conventions
// Stage names (fetch, decode, operand, and execute) are used interchangeably
// with stage numbers (1, 2, 3, 4). For instance, s2 is commonly used
// abbreviation for the stage 2 (decode)
// Many names and expressions have been taken from the Nios Embedded Processor
// 32-Bit Programmer's Reference Manual
//***************************************************************************

//***************************************************************************
//	nios_0
//
//	Module nios_0  serves as a top level module for CPU instantiation
//	It instantiates and interconects the datapath and the control unit
//	The name of this module has to be the same as the name of the Nios
//	processor in the SOPC Builder. In case when there is more processors
//	in the system, there has to exist the same number of uniquely named
//	modules, because each processor may have different set of
//	configuration options
//
module nios_0 (
	// inputs
	clk,
	d_irq,
	d_irqnumber,
	d_readdata,
	d_wait,
	i_datavalid,
	i_readdata,
	i_wait,
	reset_n,

	// outputs
	d_address,
	d_byteenable,
	d_read,
	d_write,
	d_writedata,
	i_address,
	i_flush,
	i_read
 	);

	parameter FIFO_SIZE = `FIFO_SIZE;
	parameter LOG_REGISTER_FILE_SIZE = `LOG_REGISTER_FILE_SIZE;
	parameter START_ADDRESS = `START_ADDRESS;
	parameter VECTOR_TABLE_ADDRESS = `VECTOR_TABLE_ADDRESS;

	input 			clk;
	input 			d_irq;
	input [5:0] 	d_irqnumber;
	input [31:0]	d_readdata;
	input 			d_wait;
	input 			i_datavalid;
	input [15:0]	i_readdata;
	input 			i_wait;
	input 			reset_n;
	
	output [31:0]	d_address;
	output [3:0]	d_byteenable;
	output 			d_read;
	output 			d_write;
	output [31:0]	d_writedata;
	output [31:0]	i_address;
	output 			i_flush;
	output 			i_read;

	wire 		ctrl_en;
	wire 		cwp_is_hi_limit;
	wire 		cwp_is_lo_limit;
	wire [23:0]	decoded_instr;
	wire 		decrement_cwp;
	wire 		disable_interrupts;
	wire 		flush_pipeline;
	wire 		flush_fifo;
	wire 		force_interrupt;
	wire 		force_read;
	wire 		force_trap_1;
	wire 		force_trap_2;
	wire 		increment_cwp;
	wire 		interrupt;
	wire [15:0]	ir;
	wire 		keep_pc;
	wire 		ld;
	wire 		load_nops;
	wire 		next_is_ctrl_flow_instr;
	wire 		next_is_restore;
	wire 		next_is_save;
	wire 		next_is_wrctl;
	wire 		pending_interrupt;
	wire 		pfx;	
	wire 		read_next;
	wire [31:0]	RA;
	wire 		reg_write;	
	wire 		restore;
	wire 		save;
	wire 		save_status;
	wire 		skip;
	wire 		skp0;
	wire 		skp1;
	wire 		skprnz;
	wire 		skprz;
	wire 		skps;
	wire 		st;
	wire [17:0]	status;
	wire 		trap;
	wire 		tret;
	
	control_unit the_control_unit (
		// inputs
		.clk 						(clk),
		.ctrl_en					(ctrl_en),
		.cwp_is_hi_limit			(cwp_is_hi_limit),
		.cwp_is_lo_limit			(cwp_is_lo_limit),
		.d_irq						(d_irq),
		.d_irqnumber				(d_irqnumber),
		.d_wait						(d_wait),
		.decoded_instr				(decoded_instr),
		.ir							(ir),
		.ld							(ld),
		.next_is_ctrl_flow_instr	(next_is_ctrl_flow_instr),
		.next_is_restore			(next_is_restore),
		.next_is_save				(next_is_save),
		.next_is_wrctl				(next_is_wrctl),
		.pfx						(pfx),
		.RA							(RA),
		.reset_n					(reset_n),
		.restore					(restore),
		.save						(save),
		.skp0						(skp0),
		.skp1						(skp1),
		.skprnz						(skprnz),
		.skprz						(skprz),
		.skps						(skps),
		.st							(st),
		.status						(status),
		.trap						(trap),
		.tret						(tret),

		// outputs
		.d_read						(d_read),
		.d_write					(d_write),
		.decrement_cwp				(decrement_cwp),
		.disable_interrupts			(disable_interrupts),
		.flush_pipeline				(flush_pipeline),
		.flush_fifo					(flush_fifo),
		.force_interrupt			(force_interrupt),
		.force_read					(force_read),
		.force_trap_1				(force_trap_1),
		.force_trap_2				(force_trap_2),
		.increment_cwp				(increment_cwp),
		.interrupt					(interrupt),
		.keep_pc					(keep_pc),
		.load_nops					(load_nops),
		.pending_interrupt			(pending_interrupt),
		.read_next					(read_next),
		.reg_write					(reg_write),
		.save_status				(save_status),
		.skip						(skip)
		);
		
	datapath the_datapath (
		// inputs
		.clk						(clk),
		.current_reg_write_en		(reg_write),
		.d_irqnumber				(d_irqnumber),
		.d_readdata					(d_readdata),
		.decrement_cwp				(decrement_cwp),
		.disable_interrupts			(disable_interrupts),
		.flush_pipeline				(flush_pipeline),
		.flush_fifo					(flush_fifo),
		.force_interrupt			(force_interrupt),
		.force_read					(force_read),
		.force_trap_1				(force_trap_1),
		.force_trap_2				(force_trap_2),
		.i_datavalid				(i_datavalid),
		.i_readdata					(i_readdata),
		.i_wait						(i_wait),
		.increment_cwp				(increment_cwp),
		.interrupt					(interrupt),
		.keep_pc					(keep_pc),
		.load_nops					(load_nops),
		.pending_interrupt			(pending_interrupt),
		.read_next					(read_next),
		.reset_n					(reset_n),
		.save_status				(save_status),
		.skip						(skip),

		// outputs
		.ctrl_en					(ctrl_en),
		.cwp_is_hi_limit			(cwp_is_hi_limit),
		.cwp_is_lo_limit			(cwp_is_lo_limit),
		.d_address					(d_address),
		.d_byteenable				(d_byteenable),
		.d_writedata				(d_writedata),
		.decoded_instr				(decoded_instr),
		.i_address					(i_address),
		.i_flush					(i_flush),
		.i_read						(i_read),
		.ir							(ir),
		.ld							(ld),
		.next_is_ctrl_flow_instr	(next_is_ctrl_flow_instr),
		.next_is_restore			(next_is_restore),
		.next_is_save				(next_is_save),
		.next_is_wrctl				(next_is_wrctl),
		.pfx						(pfx),
		.RA							(RA),
		.restore					(restore),
		.save						(save),
		.skp0						(skp0),
		.skp1						(skp1),
		.skprnz						(skprnz),
		.skprz						(skprz),
		.skps						(skps),
		.st							(st),
		.status_reg					(status),
		.trap						(trap),
		.tret						(tret)
	);
	defparam the_datapath.LOG_REGISTER_FILE_SIZE = LOG_REGISTER_FILE_SIZE;
	defparam the_datapath.START_ADDRESS = START_ADDRESS;
	defparam the_datapath.VECTOR_TABLE_ADDRESS = VECTOR_TABLE_ADDRESS;
	defparam the_datapath.FIFO_SIZE = FIFO_SIZE;