vga_sig.vhd

用VHDL语言编写的弹球游戏

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity vga_sig is
port(clock: in std_logic;reset:in std_logic;
     hsyncb,vsyncb:out std_logic;
     enable:out std_logic;
     xaddr,yaddr:out std_logic_vector(9 downto 0));
end vga_sig;

architecture vga of vga_sig is
    signal hcnt:std_logic_vector(9 downto 0);
    signal vcnt:std_logic_vector(9 downto 0);
    constant h_pixels:integer:=640;
    constant h_front:integer:=16;
    constant h_back:integer:=48;
    constant h_synctime:integer:=96;
    constant h_period:integer:=h_synctime+h_pixels+h_front+h_back; --800
    constant v_lines:integer:=480;
    constant v_front:integer:=10;
    constant v_back:integer:=33;
    constant v_synctime:integer:=2;
    constant v_period:integer:=v_synctime+v_lines+v_front+v_back; --525
begin
-------------------------------------------------------------------------------------------------------
    a:process(clock,reset)
    begin
        if reset='1' then
            hcnt<="0000000001";
        elsif clock'event and clock='1' then
            if hcnt<h_period then
                hcnt<=hcnt+1;
            else
                hcnt<="0000000001";
            end if;
        end if;
    end process;
-------------------------------------------------------------------------------------------------------
    b:process(clock,reset)
    begin
        if reset='1' then
            vcnt<="0000000001";
        elsif clock'event and clock='1' then
            if vcnt<v_period and hcnt=h_period then
                vcnt<=vcnt+1;
            elsif vcnt=v_period and hcnt=h_period then
                vcnt<="0000000001";
            end if;
        end if;
    end process;
-------------------------------------------------------------------------------------------------------
    c:process(clock,reset)
    begin
        if reset='1' then
            hsyncb<='1';
        elsif clock'event and clock='1' then
            if (hcnt>=h_pixels+h_front) and (hcnt<h_pixels+h_synctime+h_front) then
                hsyncb<='0';
            else
                hsyncb<='1';
            end if;
        end if;
   end process;
-------------------------------------------------------------------------------------------------------
    d:process(clock,reset)
    begin
        if reset='1' then
            vsyncb<='1';
        elsif clock'event and clock='1' then
            if (vcnt>=v_lines+v_front) and (vcnt< v_lines+v_synctime+v_front) then
                vsyncb<='0';
            else
                vsyncb<='1';
            end if;
        end if;
    end process;
-------------------------------------------------------------------------------------------------------
    e:process(clock)
    begin
        if clock'event and clock='1' then
            if hcnt>=h_pixels or vcnt>=v_lines then
                enable<='0';
            else
                enable<='1';
            end if;
        end if;
    end process;
-------------------------------------------------------------------------------------------------------
    f:process(clock,reset)
    begin
        if reset='1' then
            xaddr<="0000000001";
            yaddr<="0000000001";
        elsif clock'event and clock='1' then
            if hcnt<h_pixels then
                xaddr<=hcnt;
            end if;
            if vcnt<v_lines then
                yaddr<=vcnt;
            end if;
        end if;     
    end process;
-------------------------------------------------------------------------------------------------------
end;