and.asm

这是用VerilogHDL描述的一个8位精简指令集处理器

 ;---------------------
 ; Test for and
 ;---------------------

 org 0x0000

 ldi r0 0xaa
 ldi r1 0x55
 ldi r2 0x00
 and r1
 cmp r2
 jmpa ne error

 ldi r1 0xff
 and r1
 cmp r2
 jmpa ne error

 ldi r1 0x39
 ldi r0 0x71
 ldi r2 0x31
 and r1
 cmp r2
 jmpa ne error

 ldi r1 0x01
 ldi r0 0xff
 ldi r2 0x01
loop1:
 and r1
 cmp r2
 jmpa ne error
 ldi r0 0xff
 shl r1
 shl r2
 jmpr ne loop1

 ldi r1 0xff
 ldi r0 0xff
 ldi r2 0xff
loop1:
 and r1
 cmp r2
 jmpa ne error
 ldi r0 0xff
 shr r1
 shr r2
 jmpr ne loop1

 ldi r1 0x34
 ldi r0 0x68
 ldi r2 0x20
 and r1
 cmp r2
 jmpa ne error


 ; check all the registers

 ldi r0 0x27
 ldi r2 0x13
 ldi r3 0x03
 and r2
 cmp r3
 jmpr ne error
 
 ldi r0 0x58
 ldi r3 0xd3
 ldi r4 0x50
 and r3
 cmp r4
 jmpr ne error

 ldi r0 0x11
 ldi r4 0xee
 ldi r5 0x00
 and r4
 cmp r5
 jmpr ne error

 ldi r0 0x11
 ldi r5 0x38
 ldi r6 0x10
 and r5
 cmp r6
 jmpr ne error

 ldi r0 0x26
 ldi r6 0x82
 ldi r7 0x02
 and r6
 cmp r7
 jmpr ne error

 ldi r0 0x52
 ldi r7 0x9c
 ldi r1 0x10
 and r7
 cmp r1
 jmpr ne error

 jmpa al finish

error:
  ldi r0 0xa2
  sta r0 0x1234
  jmpr al skip

finish:
  ldi r0 0x55
  sta r0 0xffff

skip:
  nop
  nop 
  end