fifo.v

一个异步的FIFO的VERILOG程序,有测试程序

//16X16 store unit as fifo
//date:2005/6/3
//file name:fifo.v
//-------------------------------------------------------
module fifo(clk,rstp,din,writep,readp,dout,emptyp,fullp);
    input clk;                    //clk signal
    input rstp;                   //reset signal
    input[15:0] din;               //16 bit input port
    input readp;                    //read pointer
    input writep;                  //write pointer
    output [15:0] dout;            //16 bit output port
    output emptyp;                  //show store memory  empty flag
    output fullp;                  //show  store memory  full flag
    
    parameter DEPTH=2,MAX_COUNT=2'b11;
    
    reg [15:0] dout;
    reg emptyp;
    reg fullp;
    
    reg[(DEPTH-1):0] tail;         //read pointer
    reg[(DEPTH-1):0] head;         //write pointer
    reg[(DEPTH-1):0] count;         //counter
    reg[15:0] fifomem[0:MAX_COUNT];  //four   16 bit store unit 
    
   //read date
    always@(posedge clk)
       begin
           if(rstp==1)               //reset
           begin
               dout<=16'h0000;
           end
           else if(readp==1'b1&&emptyp==1'b0)  /*read valid and store memory is
                                      not empty, read out the fifo date*/                                                                        is not empty,read out date*                                   
           begin
               dout<=fifomem[tail];
           end
       end
       
       //write date
       always @(posedge clk)
       begin
           if(rstp==1'b0&&writep==1'b1&&fullp==1'b0)
           /*write signal valid and store memory is not full, 
           write the date to fifo*/
           begin
               fifomem[head]<=din;
           end
       end
       
       
    //renew head pointer
       always@(posedge clk)
       begin
           if(rstp==1'b1)    //reset valid ,set head to zero
           begin
           head<=2'b00;
       end
       
       else
       begin
           if(writep==1'b1&&fullp==1'b0)  //at write date status
           begin
               head<=head+1;              //head pointer increase one
           end
       end
   end
   
   always@(posedge clk)
   begin
       if(rstp==1'b1)                  //reset valid ,set tail pointer to zero
       begin
           tail<=2'b00;
       end
       else
       begin
           if(readp==1'b1&&emptyp==1'b0)    //at read date status
           begin
               tail<=tail+1;               //tail pointer increase one
           end
       end
   end
   
   
   //renew counter
   always@(posedge clk)
   begin
       if(rstp==1'b1)         //reset signal valid ,set counter to 0
       begin
           count<=2'b00;
       end
       else
       begin
           case({readp,writep})
               2'b00:               //no read,no write
               count<=count;
               
               2'b01:               //write pointer
               if(count!==MAX_COUNT)//counter is not reach max of store 
                                       //unit,increase one
               count<=count+1;
               
               2'b10:               //read pointer
               if(count!==2'b00)
               count<=count-1;
               
               2'b11:            //write and read  at same time.
               count<=count;    //counter does not change
       endcase
   end
   end
   
   
   //renew empty flag bit
   always @(count)
   begin
       if(count==2'b00)
       emptyp<=1'b1;
       else
       emptyp<=1'b0;
   end
   
   
   //renew fullp flag bit
   always@(count)
   begin
       if(count==MAX_COUNT)
       fullp<=1'b1;
       else
       fullp<=1'b0;
   end
   endmodule