readme.txt

来自「quartus7.1的avalon总线的测试。」· 文本 代码 · 共 33 行

altera_avalon_checksum readme version 7.1

The altera_avalon_checksum HDL design files:
altera_avalon_checksum.v - Top level module instantiates 
	checksum_task_logic, read_master and s1_slave modules

checksum_task_logic.v - Primary checksum task logic to compute 
	checksum 

read_master.v - Avalon-MM master port interface and read master 
	statemachine

s1_slave.v - Avalon-MM slave port interface and slave registers

Software files:
/inc/altera_avalon_checksum_regs.h - Defines macros to access 
	altera_avalon_checksum registers and bit-field masks

/test_software/test_checksum.c - Simple C program that exercises the 
	altera_avalon_checksum - requires onchip memory call 
	onchip_ram_64_kbytes found with most Nios II 
	standard example design.

altera_avalon_checksum_sw.tcl - For 7.1 Nios II command line flow

/HAL/inc - empty - For future expansion of checksum example 
	with HAL drivers

/HAL/src - empty - For future expansion of checksum example 
	with HAL drivers