s1_slave.v

quartus7.1的avalon总线的测试。

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module s1_slave
	(
		//Global Avalon interface siganals   
		gls_clk,
		gls_reset_n,
		//Signals for Avalon-MM slave port
		avs_s1_address,
		avs_s1_read_n,
		avs_s1_write_n,
		avs_s1_writedata,
		avs_s1_readdata,
		avs_s1_chipselect_n,
		//Signals Avalon-MM master module
		addr_reg,
		len_reg,
		go,
		read_busy,    // busy bit
		edge_pulse,   // debug -- look for busy bit transition
		// Signals transform
		result


	);

		input gls_clk;
		input gls_reset_n;
		
		input [2:0]avs_s1_address;
		input avs_s1_read_n;
		input avs_s1_write_n;
		input [31:0]avs_s1_writedata;
		output [31:0]avs_s1_readdata;
		input avs_s1_chipselect_n;
		
		output [31:0]addr_reg;
		output [15:0]len_reg;
		output go;
		input read_busy;
		output edge_pulse;   // debug -- look for busy bit transition
		input [15:0]result;

// Module contents

wire [31:0]avs_s1_readdata;


wire edge_pulse;
wire [31:0]result_32;
wire [31:0]status_32;

reg [31:0]addr_reg;
reg [15:0]len_reg;
reg [2:0]cntl_reg;
reg read_done;
reg edge_detect_reg;
reg [31:0]read_data_reg;

// drive GO bit from control register
assign go = cntl_reg[0];

//define the write register offsets
parameter	ADDR = 3'b000,
			LEN = 3'b001,
			CNTL = 3'b010,
			RESERVED1 = 3'b011;
			
//Define the read register offsets
parameter	RESULT = 3'b100,
			STATUS = 3'b101,
			RESERVED2 = 3'b110,
			RESERVED3 = 3'b111;	

// create write register block			
always @ (posedge gls_clk or negedge gls_reset_n)
begin
	if (gls_reset_n == 1'b0)
	begin
		addr_reg <= 32'h00000000;
		len_reg <= 16'h0000;
		cntl_reg <= 3'b000;
		//read_done <= 1'b1;
	end
	
	else
	begin
		if 	(avs_s1_chipselect_n == 1'b0 & avs_s1_write_n == 1'b0)  // write cycle to slave registers	
		//if 	(valid_write)  // write cycle to slave registers
		begin
			case (avs_s1_address[2:0])  
				ADDR:
				begin
					if (!read_busy)
					begin
						addr_reg <= avs_s1_writedata[31:0];
					end
					else begin
						addr_reg <= addr_reg;
					end
				end
			  	LEN:
				begin
					if (!read_busy)
					begin
						len_reg <= avs_s1_writedata[15:0];
					end
					else begin
						len_reg <= len_reg;
					end					
				end
				CNTL:
				begin
					if (!read_busy)
					begin
						cntl_reg <= avs_s1_writedata[2:0];
					end
					else begin
						cntl_reg <= cntl_reg;
					end						
				end
				default:
				begin
					addr_reg <= addr_reg;
					len_reg <= len_reg;
					cntl_reg <= cntl_reg;
				end
	
			endcase
		end
		
		if (go) // clear go bit after asserted one clock cycle
		begin
			cntl_reg[0] <= 1'b0;
		end		
	end
end

// Create read register block
always @ (posedge gls_clk or negedge gls_reset_n)
begin
	if (gls_reset_n == 1'b0)
	begin
		read_data_reg <= 32'b0;
	end
	
	else
	begin
		read_data_reg <=	(avs_s1_address == LEN)  ? { 16'h0000, len_reg[15:0] } :
							(avs_s1_address == CNTL) ? { 28'h00000000, cntl_reg[2:0] } :
							(avs_s1_address == RESULT) ? {16'h000, result[15:0]} :
							(avs_s1_address == STATUS) ? {30'h00000000, read_done, read_busy} :
							 							addr_reg;
	end
end

// Assigns read_data_reg to the slave readdata port
assign avs_s1_readdata = read_data_reg;

// negitive edge detect circuit to generate read_done bit from busy bit 
always @ (posedge gls_clk or negedge gls_reset_n)
begin
	if (gls_reset_n == 1'b0)
		begin		
			edge_detect_reg <= 'b0;
		end
	else if (gls_clk == 1'b1)
		begin
			edge_detect_reg <= read_busy;
		end
end

// Looks for negitive edge transition of busy bit compared to previous clock value
assign edge_pulse =  !(read_busy | !edge_detect_reg );		

always @ (posedge gls_clk or negedge gls_reset_n)
begin
	if (gls_reset_n == 1'b0)
		begin		
			read_done <= 'b0;
		end
	else if (edge_pulse)  // asserts DONE bit when edge detected
		begin
			read_done <= 1'b1;
		end
	else if (go)  // clear done bit when GO bit asserted
		begin
		 	read_done <= 1'b0;
		end	
	else
		begin
			read_done <= read_done;
		end		
		
		
end


endmodule