📄 buffer_comp.edn

📁 JPEG标准下图象压缩的VHDL实现工程
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   )
   (instance BU71
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      (property WRITE_MODE (string "READ_FIRST"))
      (property INIT (string "0"))
      (property SRVAL (string "0"))
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      (property INIT_2F (string "0000000000000000000000000000000000000000000000000000000000000000"))
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      (property INIT_3A (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_3B (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_3C (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_3D (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_3E (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property INIT_3F (string "0000000000000000000000000000000000000000000000000000000000000000"))
      (property WRITE_MODE (string "READ_FIRST"))
      (property INIT (string "0"))
      (property SRVAL (string "0"))
   )
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      (portRef ADDR_13_ (instanceRef B146))
    )
💿 文件大小 1441 K
👤 上传用户 ldh_ncu10
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#JPEG #VHDL #标准 #图象压缩
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