top_config_c1.vhd

用VHDL实现视频控制程序

library IEEE;
use IEEE.std_logic_1164.all;
use work.libreria_i2c.all;
-- Top encargado de la configuracion del 
-- decodificador de video

entity TOP_CONFIG_C1 is
	port (
	reloj: in STD_LOGIC;
	reset: in STD_LOGIC;
	inicio_conf: in STD_LOGIC;    
	   -- Conexiones externas del circuito configurador 
	   -- con el procesador de video.
	SDA1 : inout STD_LOGIC;   
	SCL: out STD_LOGIC;
	RESULTADO: out STD_LOGIC_VECTOR (3 downto 0);
	CONFIGURACION_OK: out STD_LOGIC
	        
	);
end TOP_CONFIG_C1;

architecture TOP_CONFIG_C1_arch of TOP_CONFIG_C1 is

COMPONENT config_procvideo1 
	port (
        	reloj: in STD_LOGIC;
        	reset: in STD_LOGIC;
        	inicio: in STD_LOGIC;
        	SCLint: buffer STD_LOGIC;
        	OESCL: out STD_LOGIC;
		OESDA: out STD_LOGIC;
		bit_sal: out STD_LOGIC;
		SDAent1: in STD_LOGIC;
		resultado: out STD_LOGIC_VECTOR (3 downto 0);
		configuracion_val: out STD_LOGIC
	);
end component;


-- Senales de interconexion del circuito de configuracion del procesador de video
-- con sus componentes triestado.
signal SCLint: STD_LOGIC;
signal OESCL: STD_LOGIC;
signal OESDA: STD_LOGIC;
signal bit_sal: STD_LOGIC;
signal aux_SDAent1: STD_LOGIC;

begin

--------------------------------------------------------------------
---------------------- PROCESADOR DE VIDEO -------------------------
--------------------------------------------------------------------
-- Instanciamos el circuito configurador.

CONFIGURADOR_PROCVIDEO: config_procvideo1
    	port map (
	        reloj =>  reloj,
       	  	reset => reset,
	        inicio => inicio_conf,
	        SCLint => SCLint,
	        OESCL => OESCL,
	        OESDA => OESDA,
	        bit_sal => bit_sal,
	        SDAent1 => aux_SDAent1,
	   	resultado=> resultado,
		configuracion_val=>configuracion_ok  	
        );

BUFFER_SCL: bufferZ
	port map (
		ent => SCLint,
		OE => OESCL,
		sal => SCL
	);
	
BUFFER1_IO_SDA: IOpad
	port map (
		OE => OESDA,
		SAL => bit_sal,
		ENT => aux_SDAent1,
		PAD => SDA1
	);

end TOP_CONFIG_C1_arch;