interruptor.vhd

来自「用VHDL实现视频控制程序」· VHDL 代码 · 共 42 行

library IEEE;
use IEEE.std_logic_1164.all;

entity Interruptor is
    port (
        clk: in STD_LOGIC;
        resetz: in STD_LOGIC;
        enable:in STD_LOGIC;
        turno: out STD_LOGIC
    );
end Interruptor;

architecture Interruptor_arch of Interruptor is

signal p_turno,a_turno:std_logic;

begin

p:process(a_turno,enable)
begin
    if(enable='1')then    
    	p_turno<= not a_turno;
    else
    	p_turno<=a_turno;
    end if;

end process;

sinc:process(clk, resetz)
begin

    if(resetz='0')then
    	a_turno<='0';
    elsif(clk'event and clk='1')then
    	a_turno<=p_turno;
    end if;
end process;

turno<=a_turno;

end Interruptor_arch;