config_procvideo1.vhd

用VHDL实现视频控制程序

-- Definicion de la arquitectura del circuito de configuracion del procesador de video.
library IEEE;
use IEEE.std_logic_1164.all;
use work.libreria_i2c.all;

entity config_procvideo1 is
	port (
        	reloj: in STD_LOGIC;
        	reset: in STD_LOGIC;
        	inicio: in STD_LOGIC;
        	SCLint: buffer STD_LOGIC;
        	OESCL: out STD_LOGIC;
		OESDA: out STD_LOGIC;
		bit_sal: out STD_LOGIC;
		SDAent1: in STD_LOGIC;
		resultado: out STD_LOGIC_VECTOR (3 downto 0);
		configuracion_val: out STD_LOGIC
	);
end config_procvideo1;

architecture config_procvideo1_arch of config_procvideo1 is
-- SENALES DE INTERCONEXION DE COMPONENTES.
signal inicio_trans: STD_LOGIC;
signal fin_esp64_prot: STD_LOGIC;
signal fin_esp128_prot: STD_LOGIC;
signal punt_bit: STD_LOGIC_VECTOR (2 downto 0);
signal punt_byte: STD_LOGIC_VECTOR (1 downto 0);
signal carga_datos: STD_LOGIC;
signal inc_punt_bit: STD_LOGIC;
signal inc_punt_byte: STD_LOGIC;
signal reset_punt_byte: STD_LOGIC;
signal ENespera64_prot: STD_LOGIC;
signal ENespera128_prot: STD_LOGIC;
signal ready: STD_LOGIC;
signal preset_SCL: STD_LOGIC;
signal reset_SCL: STD_LOGIC;
signal reset_SDA: STD_LOGIC;
signal load_SDA: STD_LOGIC;
signal subdir: STD_LOGIC_VECTOR (7 downto 0);
signal reg_subdir: STD_LOGIC_VECTOR (7 downto 0);
signal dato: STD_LOGIC_VECTOR (7 downto 0);
signal reg_dato: STD_LOGIC_VECTOR (7 downto 0);
signal DIR_ESC_ESCLAVO: STD_LOGIC_VECTOR (7 downto 0);
signal byte: STD_LOGIC_VECTOR (7 downto 0);
signal bit_SDA: STD_LOGIC;
signal fin_esp128_gen: STD_LOGIC;
signal punt_mem: STD_LOGIC_VECTOR (6 downto 0);
signal ENespera128_gen: STD_LOGIC;
signal reset_punt_mem: STD_LOGIC;
signal inc_punt_mem: STD_LOGIC;
signal SDAent: STD_LOGIC;
signal N_SDAent: STD_LOGIC;

begin
-- Comenzamos la instanciacion de componentes.
FSM_PROTOCOLO_I2C: FSM_I2C
	port map (
		reloj => reloj,
		reset => reset,
		trans => inicio_trans,
		fin_espera64 => fin_esp64_prot,
		fin_espera128 => fin_esp128_prot,
		puntero => punt_bit,
		SDAent => SDAent1,
		SCL => SCLint,
		punt_byte => punt_byte,
		load_new => carga_datos,
		inc_punt => inc_punt_bit,
		inc_sel_byte => inc_punt_byte,
		reset_sel_byte => reset_punt_byte,
		ENespera64 => ENespera64_prot,
		ENespera128 => ENespera128_prot,
		ready => ready,
		preset_div => preset_SCL,
		reset_div => reset_SCL,
		OESCL => OESCL,
		reset_bit => reset_SDA,
		load_bit => load_SDA,
		OESDA => OESDA
	);								

GEN_SCL: divisor 
	port map (
		reset => reset,	
		reloj => reloj,
		clear => reset_SCL,
		set => preset_SCL,
		SCL => SCLint
	);
	
REGISTRO_SUBDIR: registro
	port map (
		reset => reset,
		reloj => reloj,
		LE => carga_datos,
		dat_in => subdir,
		dat_out => reg_subdir
	);

REGISTRO_DATO: registro
	port map (
		reset => reset,
		reloj => reloj,
		LE => carga_datos,
		dat_in => dato,
		dat_out => reg_dato
	);
	
MUX_SEL_BYTE: mux_byte
	port map (
		byte2 => reg_dato,
		byte1 => reg_subdir,
		byte0 => DIR_ESC_ESCLAVO,
		sel => punt_byte,
		byte_sal => byte
	);
	
DIR_ESC_ESCLAVO <= X"4A";

PUNTERO_BYTE: contador_byte
	port map (
		reset => reset,
		reloj => reloj,
		clear => reset_punt_byte,
		inc => inc_punt_byte,
		cont => punt_byte
	);
	
MUX_SEL_BIT: mux
	port map (
		ent => byte,
		sel => punt_bit,
		sal => bit_SDA
	);
	
PUNTERO_BIT: contador
	port map (
		reset => reset,
		reloj => reloj,
		inc => inc_punt_bit,
		cont => punt_bit
	);
	
SALIDA_SDA: tx_bit
	port map (
		reset => reset,
		reloj => reloj,
		clear => reset_SDA,
		D => bit_SDA,
		LE => load_SDA,
		Q => bit_sal
	);

ESPERA64_PROT: cont_espera64
	port map (
		reset => reset,
		reloj => reloj,
		enable => ENespera64_prot,
		fin => fin_esp64_prot
	);
	
ESPERA128_PROT: cont_espera128
	port map (
		reset => reset,
		reloj => reloj,
		enable => ENespera128_prot,
		fin => fin_esp128_prot
	);

FSM_GENERADORA_DATOS: FSM_gen_datos
	port map (
		reloj => reloj,
		reset => reset,
		inicio => inicio,
		ready => ready,
		punt_byte => punt_byte,
		fin_espera128 => fin_esp128_gen,
		punt_mem => punt_mem,
		trans => inicio_trans,
		dir => subdir,
		dato => dato,
		ENespera128 => ENespera128_gen,
		reset_punt_mem => reset_punt_mem,
		inc_punt_mem => inc_punt_mem,
		resultado => resultado,
		conf_valida=>configuracion_val
	);			

ESPERA128_GEN: cont_espera128
	port map (
		reset => reset,
		reloj => reloj,
		enable => ENespera128_gen,
		fin => fin_esp128_gen
	);

PUNTERO_DATOS_CONF: contador_REG
	port map (
		reset => reset,
		reloj => reloj,
		clear => reset_punt_mem,
		inc => inc_punt_mem,
		cont => punt_mem
	);
		
end config_procvideo1_arch;