selecc_pixel.vhd

用VHDL实现视频控制程序

library IEEE;
use IEEE.std_logic_1164.all;

entity selecc_pixel is
    port (
        pix0: in STD_LOGIC_VECTOR (7 downto 0);
        pix1: in STD_LOGIC_VECTOR (7 downto 0);
        clk: in STD_LOGIC;
        resetz: in STD_LOGIC;
        enable: in STD_LOGIC;
        pix_out: out STD_LOGIC_VECTOR (7 downto 0);
        captura: out STD_LOGIC        
    );
end selecc_pixel;

architecture selecc_pixel_arch of selecc_pixel is

type estado is (reposo,compara,obviar);
signal actual,futuro: estado;
signal p_salida: std_logic_vector (7 downto 0);
signal p_captura:std_logic;

begin

p: process (enable,pix0,pix1,p_salida,actual)

begin

   p_captura<='0';
   
   CASE actual is
   	
   	when reposo =>
   	    p_salida<=(OTHERS=>'0');
   	    if(enable='1')then
   	       futuro<=compara;
   	    else
   	       futuro<=reposo;
   	    end if;
   	when compara =>
   	    if(pix0=pix1)then            -- Si dos pixeles consecutivos son iguales,
   	       p_salida<=pix0;           -- se elige el primero y se descarta el tercero   
   	       futuro<=obviar;
   	       p_captura<='1';           --Saca la senal captura
	    else
	       futuro<=compara;          -- Si los dos pixeles no son iguales, se elige el primero 
	       p_salida<=pix0;           -- y se comparan el segundo y el tercero
	    end if;   	 
	when obviar =>
   	    p_salida<=pix0;
	    futuro<=compara;
end case;

end process p;

sinc: process (resetz, clk)
  BEGIN
	if(resetz='0') then   -- Reset a nivel bajo
	   actual <= reposo;
	   pix_out<=(others=>'0');
	   captura<='0';
	elsif(clk'event and clk = '1')then
	   actual <= futuro;
	   pix_out<=p_salida;
	   captura<=p_captura;
	end if;
END process sinc;



end selecc_pixel_arch;