controla_enable.vhd

用VHDL实现视频控制程序

library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

entity controla_enable is
    port (
        enable: in STD_LOGIC;
        clk: in STD_LOGIC;
        resetz: in STD_LOGIC;
        captura: in STD_LOGIC;
        enable_selecc: out STD_LOGIC;
	enable_yuv: out STD_LOGIC;
	enable_rgb: out STD_LOGIC;
	contador: out STD_LOGIC_VECTOR(1 downto 0)
    );
end controla_enable;

architecture controla_enable_arch of controla_enable is

type estado1 is (reposo,selecc);
type estado2 is (reposo,est1);
signal actual1,futuro1:estado1;
signal p_enable_selecc,p_enable_yuv,p_enable_rgb :std_logic;
signal actual2,futuro2:estado2;
signal p_cuenta, cuenta:std_logic_vector(1 downto 0);

begin

p1: process(actual1,enable)
begin
  p_enable_selecc<='0';

  case actual1 is
      when reposo =>
         if(enable='1')then
           futuro1<=selecc;      
	 else
	   futuro1<=reposo;
	 end if;
       when selecc =>
         p_enable_selecc<='1';           --enable del selector de pixeles retrasado un ciclo
         if(enable='1')then
         	futuro1<=selecc;
         else
         	futuro1<=reposo;
         end if;
   end case;
end process;

p2: process(actual2,captura,cuenta)
begin
   p_enable_yuv<='0';
   p_enable_rgb<='0';
   p_cuenta<=cuenta;
   
   case actual2 is
   	when reposo =>
   	    if(captura='1')then
   	    	p_enable_yuv<='1';        --enable del yuv a la vez de captura
   	    	futuro2<=est1;
   	    else
   	    	p_enable_yuv<='0';
   	    	futuro2<=reposo;
   	    end if;

	when est1 =>
	    if(cuenta=3)then
	    	p_cuenta<=(OTHERS=>'0'); 
	    	p_enable_rgb<='1';       --enable del rgb a la vez de captura
	    else
	        p_cuenta<=cuenta + 1;	    
	        p_enable_rgb<='0';
	    end if;
	    futuro2<=reposo;
   end case;
end process;	    


--Proceso de sincronismo

sinc: process (resetz, clk)
  BEGIN
	if(resetz='0') then   -- Reset a nivel bajo
	   actual1<= reposo;
  	   actual2<= reposo;
   	   enable_selecc<='0';
	   enable_yuv<='0';
	   enable_rgb<='0';
	   cuenta<=(OTHERS => '0');
	elsif(clk'event and clk = '1')then
	   actual1<= futuro1;
  	   actual2<= futuro2;
   	   enable_selecc<=p_enable_selecc;
	   enable_yuv<=p_enable_yuv;
	   enable_rgb<=p_enable_rgb;
	   cuenta<=p_cuenta;
	end if;
END process sinc;

contador<=cuenta;

end controla_enable_arch;