minitoprincipal.vhd

用VHDL实现视频控制程序

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity top_principal is
    port (
        href:in STD_LOGIC;                     --indica comienzo y final de linea
	VPO: in STD_LOGIC_VECTOR (7 downto 0); --pixeles de la camara
        llc: in STD_LOGIC;                     --reloj de pixeles
        clk: in STD_LOGIC;                     --reloj
        odd: in STD_LOGIC;                     --indica el principio y mitad de pantalla
        resetz: in STD_LOGIC;                  --reset a nivel bajo
        
        OP: in STD_LOGIC_VECTOR(2 downto 0);   --indica el tipo de operacion
        
       	inicio_conf_top: in STD_LOGIC;         --senales de configuracion del digitalizador
	SDA1_top : inout STD_LOGIC;   
	SCL_top: out STD_LOGIC;

	CONFIGURACION_OK_top: out STD_LOGIC;   --indica que el digitalizador esta bien 
					       --configurado

        
        cap: in std_logic;		
        hsync: out STD_LOGIC;                  --senales de la interfaz
        vsync: out STD_LOGIC;
        resetchip: out STD_LOGIC;
        r: out STD_LOGIC_VECTOR (1 downto 0);
        g: out STD_LOGIC_VECTOR (1 downto 0);
        b: out STD_LOGIC_VECTOR (1 downto 0);
        
        salida: in std_logic                   --senal para depurar la interfaz
        

    );
end top_principal;

architecture top_principal_arch of top_principal is


component capture_virtex is		--para depurar
	port(
		cap: in std_logic;      --memorizar estado
		clk: in std_logic
		);
end component;

--Buffer para el reloj

COMPONENT IBUFG
    port(
    	I: in STD_LOGIC;
    	O: out STD_LOGIC
    	);
end component;

component clkdll is	--componente de libreria virtex ecualiza retrasos

port (
	clkin : in std_logic;
	clkfb: in std_logic;
	rst: in std_logic;
	clk0: out std_logic;
	clk90: out std_logic;
	clk180: out std_logic;
	clk270: out std_logic;
	clk2x: out std_logic;
	clkdv: out std_logic;
	locked: out std_logic
	);
end component;

--Bloque de configuracin del digitalizador

component TOP_CONFIG_C1 is			
	port (
	reloj: in STD_LOGIC;
	reset: in STD_LOGIC;
	inicio_conf: in STD_LOGIC;
	   -- Conexiones externas del circuito configurador
	   -- con el procesador de video.
	SDA1 : inout STD_LOGIC;
	SCL: out STD_LOGIC;
	RESULTADO: out STD_LOGIC_VECTOR (3 downto 0);
	CONFIGURACION_OK: out STD_LOGIC

	);
end component;


--Buffer para el reloj

component bufg
   port(
	i:in std_logic;
	o : out std_logic
	);
end component;	


--Bloque para sincronizarse con el principio de la pantalla

component sincronismo_pantalla is
	PORT(
              href: IN std_logic;
	      resetz:IN std_logic;
	      clk: IN std_logic;
	      configuracion_ok: IN std_logic;
	      ODD: IN std_logic;
	      llc: IN std_logic;
              habilit_adapt:OUT std_logic

	    );
END component;


--Bloque que indica los pixeles con los que nos quedamos. Adapta la resolucion del
--digitalizador a la resolucion de la pantalla

component adaptador is
   PORT(
        resetz:IN std_logic;
        clk: IN std_logic;
        habilit_adapt: IN std_logic;
        habilit_reg: OUT std_logic;
        finalpantalla:OUT std_logic
       );
end component;

--Registro para almacenar pixeles de tamano variable

component registro_pixel is
    generic ( N:integer:=8 );
    port (
        PIXEL_IN: in STD_LOGIC_VECTOR (N-1 downto 0);
        PIXEL_OUT: out STD_LOGIC_VECTOR (N-1 downto 0);
        Enable: in STD_LOGIC;
        clk: in STD_LOGIC;
        resetz: in STD_LOGIC
    );
end component;


--Bloque para validar el pixel a partir de sus muestras

component selecc_pixel is
    port (
        pix0: in STD_LOGIC_VECTOR (7 downto 0);
        pix1: in STD_LOGIC_VECTOR (7 downto 0);
        clk: in STD_LOGIC;
        resetz: in STD_LOGIC;
        enable: in STD_LOGIC;
        pix_out: out STD_LOGIC_VECTOR (7 downto 0);
        captura: out STD_LOGIC
    );
end component;


--Bloque para retrasar la senal de enable convenientemente

component controla_enable is
    port (
        enable: in STD_LOGIC;
        clk: in STD_LOGIC;
        resetz: in STD_LOGIC;
        captura: in STD_LOGIC;
        enable_selecc: out STD_LOGIC;
	enable_yuv: out STD_LOGIC;
	enable_rgb: out STD_LOGIC;
	contador: out STD_LOGIC_VECTOR(1 downto 0)
    );
end component;


--Bloque que habilita la interfaz

component controla_inter is
    port (
        clk: in STD_LOGIC;
        resetz: in STD_LOGIC;
        habilita: in STD_LOGIC;
        conf_ok: in STD_LOGIC;
        odd: in std_logic;
        habilita_vga: out STD_LOGIC;
        clear_h: out std_logic;
        clear_v: out std_logic
    );
end component;


--Bloque de la interfaz

component interfaz is
    port (
        clk: in STD_LOGIC;
        resetz: in STD_LOGIC;
        data: in STD_LOGIC_VECTOR(5 downto 0);
        habilitador: in STD_LOGIC;
	clear_h: in STD_LOGIC;
	clear_v: in STD_LOGIC;
        href:in STD_LOGIC;
        selecc: in STD_LOGIC;
        hsync: out STD_LOGIC;
        r: out STD_LOGIC_VECTOR (1 downto 0);
        g: out STD_LOGIC_VECTOR (1 downto 0);
        b: out STD_LOGIC_VECTOR (1 downto 0);
        vsync: out STD_LOGIC );
end component;


--Bloque que detecta de forma sincrona los flancos del LLC

component flanco_LLC is
   port(
        e: IN std_logic;
        clk: IN std_logic;
        resetz: IN std_logic;
        s2: OUT std_logic
   );
end component;


--Bloque que se utiliza para conmutar entre los dos pixeles en RGB

component Interruptor is
    port (
        clk: in STD_LOGIC;
        resetz: in STD_LOGIC;
        enable: in STD_LOGIC;
        turno: out STD_LOGIC
    );
end component;

--Bloque convertidor de YUV a RGB

component yuv is 
    port(
	y1,u,v,y2: in std_logic_vector(7 downto 0);
	r1,g1,b1: out std_logic_vector(1 downto 0);
	r2,g2,b2: out std_logic_vector(1 downto 0));
end component;

--Bloque para el procesamiento de los pixeles

component Proc is
    port (
        Pix_IN: in STD_LOGIC_VECTOR (5 downto 0);
        OP: in STD_LOGIC_VECTOR (2 downto 0);
        Pix_OUT: out STD_LOGIC_VECTOR (5 downto 0)
    );
end component;





--senales 

signal ckfb,ck0,ck2:std_logic;
signal iclkin:std_logic;
signal ireset:std_logic;
signal conf_ok,habilita_sinc,habilita_en,habilita_inter,habilita_selecc:std_logic;


signal llc_sal: std_logic;
signal uno:std_logic;
signal fin_pantalla:std_logic;

signal buf0,buf1,buf2,buf3,y1,u,v,y2:std_logic_vector(7 downto 0);

signal r1,g1,b1,r2,b2,g2:std_logic_vector(1 downto 0);
signal pixel_vga,pixel_out,rgb1,rgb2,pix1,pix2:std_logic_vector(5 downto 0);

signal captura,turno:std_logic;
signal enable_pix0,enable_pix1,enable_pix2,enable_pix3: std_logic;
signal enable_yuv,enable_rgb,enable_vga,enable_selecc:std_logic;
signal contador:std_logic_vector(1 downto 0);
signal clear_h,clear_v:std_logic;



begin
ireset<=not resetz;
resetchip <= resetz;
uno<='1';


bffb: bufg

port map( i=>ckfb,o=>ck0);


U1: IBUFG
   port map(
   	I=>clk,
   	O=>iclkin
   	);
   	
ckdll: clkdll
port map (
	clkin =>iclkin,
	clkfb=>ck0,
	rst=>ireset,
	clk0=>ckfb,
	clk90=>open,
	clk180=>open,
	clk270=>open,
	clk2x=>ck2,
	clkdv=>open,
	locked=>open
	);
capvtx: capture_virtex
	port map(cap=>cap ,clk=>ck0);

configuracion: top_config_c1
	port map(reloj=>ck0,reset=>ireset,inicio_conf=>inicio_conf_top,SDA1=>SDA1_top,SCL=>SCL_top,RESULTADO=>OPEN,
	CONFIGURACION_OK=>conf_ok);---------tiene reset a nivel alto     !!!!!NOTA:RESULTADO_TOP AL AIRE!!!

flanco: flanco_LLC
        port map(clk=>ck2,e=>llc,resetz=>resetz, s2=>llc_sal);

sincronismo: sincronismo_pantalla
        port map(href=>href,clk=>ck0,resetz=>resetz,configuracion_ok=>conf_ok,odd=>odd,
	habilit_adapt=>habilita_sinc,llc=>llc_sal);


adaptador_resoluc: adaptador
        port map(resetz=>resetz, clk=>ck0, habilit_adapt=>habilita_sinc, 
        habilit_reg=>habilita_en,finalpantalla=>fin_pantalla);


reg_buf0: REGISTRO_PIXEL
	generic map(N=>8)
	port map(clk=>ck2,resetz=>resetz,PIXEL_IN=>VPO,PIXEL_OUT=>buf0,enable=>uno);
	
reg_buf1: REGISTRO_PIXEL
	generic map(N=>8)
	port map(clk=>ck2,resetz=>resetz,PIXEL_IN=>buf0,PIXEL_OUT=>buf1,enable=>habilita_en);

reg_buf2: REGISTRO_PIXEL
	generic map(N=>8)
	port map(clk=>ck2,resetz=>resetz,PIXEL_IN=>buf1,PIXEL_OUT=>buf2,enable=>habilita_en);


selecciona: selecc_pixel 
        port map(clk=>ck2,resetz=>resetz,enable=>habilita_selecc,pix0=>buf0,pix1=>buf1,
        pix_out=>buf3,captura=>captura);

enable_pix0<= enable_yuv and ((not contador(0)) and (not contador(1)));
enable_pix1<= enable_yuv and (contador(0) and (not contador(1)));
enable_pix2<= enable_yuv and ((not contador(0)) and contador(1));
enable_pix3<= enable_yuv and contador(0) and contador(1);

reg_PIX0: REGISTRO_PIXEL
	generic map(N=>8)
	port map(clk=>ck2,resetz=>resetz,PIXEL_IN=>buf3,PIXEL_OUT=>y1,enable=>enable_pix0);

reg_PIX1: REGISTRO_PIXEL
	generic map(N=>8)
	port map(clk=>ck2,resetz=>resetz,PIXEL_IN=>buf3,PIXEL_OUT=>u,enable=>enable_pix1);

reg_PIX2: REGISTRO_PIXEL
	generic map(N=>8)
	port map(clk=>ck2,resetz=>resetz,PIXEL_IN=>buf3,PIXEL_OUT=>y2,enable=>enable_pix2);

reg_PIX3: REGISTRO_PIXEL
	generic map(N=>8)
	port map(clk=>ck2,resetz=>resetz,PIXEL_IN=>buf3,PIXEL_OUT=>v,enable=>enable_pix3);

yuv_conv: yuv 
	port map(
	y1=>y1,u=>u,v=>v,y2=>y2,
	r1=>r1,g1=>g1,b1=>b1,
	r2=>r2,g2=>g2,b2=>b2
	);

rgb1(5 downto 4)<=r1;
rgb1(3 downto 2)<=g1;
rgb1(1 downto 0)<=b1;
	
rgb2(5 downto 4)<=r2;
rgb2(3 downto 2)<=g2;
rgb2(1 downto 0)<=b2;
	

reg_RGB1: REGISTRO_PIXEL
	generic map(N=>6)
	port map(clk=>ck2,resetz=>resetz,PIXEL_IN=>rgb1,PIXEL_OUT=>pix1,enable=>enable_rgb);

reg_RGB2: REGISTRO_PIXEL
	generic map(N=>6)
	port map(clk=>ck2,resetz=>resetz,PIXEL_IN=>rgb2,PIXEL_OUT=>pix2,enable=>enable_rgb);


gen_int: interruptor
	port map(clk=>ck0,resetz=>resetz,turno=>turno,enable=>enable_vga);

pixel_out<= pix1 when turno='0' else pix2;

Procesado:Proc
	port map(Pix_IN=>pixel_out,OP=>OP,Pix_OUT=>pixel_vga);
	
interfaz_vga: interfaz
	port map(clk=>ck0,resetz=>resetz,clear_h=>clear_h,clear_v=>clear_v,href=>href,
	Data=>pixel_vga,habilitador=>enable_vga,selecc=>salida,
	hsync=>hsync,r=>r,g=>g,b=>b,vsync=>vsync);
	
cont_vga: controla_inter
    port map(
        clk=>ck0,
        resetz=>resetz,
        habilita=>habilita_en,
        conf_ok=>conf_ok,
        odd=>odd,
        habilita_vga=>enable_vga,
        clear_h=>clear_h,
        clear_v=>clear_v
    );


controla: controla_enable
	port map(enable=> habilita_en,
        clk=>ck2,
        resetz=>resetz,
        captura=>captura,
        enable_selecc=>enable_selecc,
	enable_yuv=>enable_yuv,
	enable_rgb=>enable_rgb,
	contador=>contador
);

CONFIGURACION_OK_TOP<=conf_ok;


end top_principal_arch;