controla_inter.vhd

用VHDL实现视频控制程序

library IEEE;
use IEEE.std_logic_1164.all;

entity controla_inter is
    port (
        clk: in STD_LOGIC;
        resetz: in STD_LOGIC;
        habilita: in STD_LOGIC;
        conf_ok: in STD_LOGIC;
        odd: in std_logic;
        habilita_vga: out STD_LOGIC;
        clear_h: out std_logic;
        clear_v: out std_logic
    );
end controla_inter;

architecture controla_inter_arch of controla_inter is

type estado1 is (reposo1,encendido);
type estado2 is (reposo2,espera2);
type estado3 is (reposo3,espera3);
signal p_inter,p_clear_h,p_clear_v:std_logic;
signal actual1,sig1:estado1;
signal actual2,sig2:estado2;
signal actual3,sig3 :estado3;



begin
  
sinc: process (clk,resetz)

begin
  
   if(resetz='0')then
    habilita_vga<='0';
    actual1<=reposo1;
    actual2<=reposo2;
    actual3<=reposo3;        
    clear_h<='0';   
    clear_v<='0';
   elsif (clk='1' and clk'event)then
    habilita_vga<=p_inter;
    actual1<=sig1;
    actual2<=sig2;
    actual3<=sig3;
    clear_h<=p_clear_h;   
    clear_v<=p_clear_v;
   end if;
 
end process sinc;  
  
minimaq1: process(habilita,conf_ok,actual1)

begin
        
   case actual1 is
      
        when reposo1 =>
           
           if(conf_ok='1' and habilita='1')then
           	p_inter<='1';                    --habilita la interfaz
           	sig1<=encendido;
           else
                p_inter<='0';                   
                sig1<=reposo1;
	   end if;

	when encendido =>
	   p_inter<='1';                        -- y la deja habilitada
	   sig1<=encendido;
    end case;
    
end process minimaq1;

--Clear horizontal. Sincronizo hsync con href

minimaq2: process(habilita,actual2)
  
begin
    case actual2 is
      when reposo2  =>
       
        if(habilita='0')then
           p_clear_h<='1';
           sig2<=espera2;
        else
           p_clear_h<='0';
           sig2<=reposo2;
        end if;
      when espera2 =>
         p_clear_h<='1';
         if (habilita='1')then
           sig2<=reposo2;
         else
           sig2<=espera2;
         end if;
     end case;

end process minimaq2;


--Clear vertical. Sincronizo vsync con odd.

minimaq3: process (odd,actual3)

begin
    case actual3 is
      when reposo3  =>
       
        if(odd='1')then
           p_clear_v<='0';
           sig3<=reposo3;
        else
           p_clear_v<='0';
           sig3<=espera3;
        end if;
      when espera3 =>
         if (odd='1')then
 	   p_clear_v<='1';        
           sig3<=reposo3;
         else
           p_clear_v<='0';
           sig3<=espera3;
         end if;
     end case;
end process minimaq3;      

end controla_inter_arch;