adaptador_resolucion.vhd

来自「用VHDL实现视频控制程序」· VHDL 代码 · 共 75 行

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;

ENTITY adaptador IS
   PORT(resetz:IN std_logic;
        clk: IN std_logic;
        habilit_adapt: IN std_logic;
        habilit_reg: OUT std_logic;
	finalpantalla: OUT std_logic
       );
end entity adaptador;

ARCHITECTURE adaptador_arch OF adaptador IS
   signal p_habilitador: std_logic;
   signal linea,ancho,p_linea,p_ancho: integer;
   signal p_final: std_logic;
BEGIN

--Proceso de sincronismo

sinc: process (resetz,clk)
  BEGIN
     if(resetz='0')then
       habilit_reg<='0';
       linea<=0;
       ancho<=0;
       finalpantalla<='1';     
     elsif(clk'event and clk='1')then
       habilit_reg<=p_habilitador;
       linea<=p_linea;
       ancho<=p_ancho;
       finalpantalla<=p_final;
     end if;
end process sinc;

p_final<='0' when (linea<480) else '1';

adapt: process(habilit_adapt,ancho,linea)
  BEGIN
 
     if(habilit_adapt='1')then
         if(ancho<(2*320))then    --resolucion horizontal pantalla 320, dos bytes por pixel
           if(linea<480)then      --resolucion vertical pantalla 480
             p_habilitador<='1';
           else
             p_habilitador<='0';
           end if;
         p_ancho<=ancho+1;
	 p_linea<=linea;
         elsif(ancho<((2*720)-1))then --resolucion horizontal digitalizador 720
           p_habilitador<='0';
           p_ancho<=ancho+1;
	   p_linea<=linea;
         else
	   if(linea<524)then       --resolucion vertical digitalizador 525
	      p_habilitador<='0';
	      p_ancho<=0;
              p_linea<=linea+1;
	   else
	      p_habilitador<='0';
	      p_ancho<=0;
	      p_linea<=0;
           end if;           
         end if;
     else
         p_habilitador<='0';
         p_linea<=0;
	 p_ancho<=ancho;
     end if;
end process adapt;

end architecture;