gencolorversionantonio.vhd

用VHDL实现视频控制程序

library IEEE;
use IEEE.std_logic_1164.all;

entity Gencolor is
    port (
	habilitador: in STD_LOGIC;
        blank_h: in STD_LOGIC;
        blank_v: in STD_LOGIC;
        Data: in STD_LOGIC_VECTOR (5 downto 0);
        R: out STD_LOGIC_VECTOR (1 downto 0);
        G: out STD_LOGIC_VECTOR (1 downto 0);
        B: out STD_LOGIC_VECTOR (1 downto 0)
    );
end Gencolor;

architecture Gencolor_arch of Gencolor is

begin

gen: process(blank_h,blank_v,data,habilitador)
begin
        if(blank_h='1' or blank_v='1' or habilitador='0')then
            R<="00";
            G<="00";
            B<="00";
        else
           R<= data(5 DOWNTO 4);
           G<= data(3 DOWNTO 2);
           B<= data(1 DOWNTO 0);
        end if;
end process gen;

end Gencolor_arch;