contador.vhd

用VHDL实现视频控制程序

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity contador_vga is
    generic(N: integer:= 8;satur:integer:=511);
    port (
        clk: in STD_LOGIC;
        enable: in STD_LOGIC;
        resetz: in STD_LOGIC;
        clear: in STD_LOGIC;
        Q: out STD_LOGIC_VECTOR (N DOWNTO 0)
        );
end contador_vga;

architecture contador_vga_arch of contador_vga is

signal p_cuenta,cuenta:integer;


begin

--Proceso de sincronismo

sinc:process(resetz,clk)
     begin 
        if(resetz='0')then
     	   p_cuenta<=0;
     	elsif(clk='1' and clk'event)then
     	   if(clear='1')then
     	   p_cuenta<=0;
     	   else
           p_cuenta<=cuenta;
           end if;
        end if;
      end process sinc;


cont:process(enable,p_cuenta)
     begin
        if(enable='1')then
           if(p_cuenta=satur)then
            cuenta<=0;
           else 
            cuenta<=p_cuenta+1;
           end if; 
        else
           cuenta<=p_cuenta;   
        end if;
Q<=conv_std_logic_vector(p_cuenta,Q'length);
end process cont;
end contador_vga_arch;