add888.vhd

VHDL设计FIR滤波器 基于QUARTUS和MATLAB

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
ENTITY add888 is
PORT(clk : in STD_LOGIC;
     Din1:in signed (15 downto 0);
     Din2:in signed (15 downto 0); 
     Dout:out signed(7 downto 0));
END add888;
ARCHITECTURE a of add888 is
SIGNAL s1: signed(7 downto 0);
SIGNAL s2: signed(7 downto 0);
BEGIN
    s1<=(Din1(15 downto 8));
    s2<=(Din2(15 downto 8));
PROCESS(Din1,Din2,clk)
BEGIN
if clk'event and clk='1' then
Dout<=s1+s2;
end if;
end process;
end a;