mult162.vhd

VHDL设计FIR滤波器 基于QUARTUS和MATLAB

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY mult162 is
PORT
( clk :  IN STD_LOGIC;
  Din :  IN SIGNED (8 DOWNTO 0);
 Dout :  OUT SIGNED (15 DOWNTO 0));
END mult162;
--128+32+2
ARCHITECTURE a OF mult162 IS
SIGNAL s1 : SIGNED (15 DOWNTO 0);
SIGNAL s2 : SIGNED (13 DOWNTO 0);
SIGNAL s3 : SIGNED (9 DOWNTO 0);
SIGNAL s4 : SIGNED (15 DOWNTO 0);

BEGIN
P1:process(Din)
BEGIN
s1(15 DOWNTO 7)<=Din;
s1( 6 DOWNTO 0)<="0000000";
s2(13 DOWNTO 5)<=Din;
s2( 4 DOWNTO 0)<="00000";
s3( 9 DOWNTO 1)<=Din;
s3( 1 )<='0';
if Din(8)='0' then 
s4<=('0'&s1(15 downto 1))+("000"&s2(13 DOWNTO 1))+("0000000"&s3(9 DOWNTO 1));

else 
s4<=('1'&s1(15 downto 1))+("111"&s2(13 DOWNTO 1))+("1111111"&s3(9 DOWNTO 1));

end if;
end process;
P2: PROCESS(clk)
BEGIN
if clk'event and clk='1' then
Dout<=s4;
end if;
END PROCESS;
END a;