fir.map.rpt

VHDL设计FIR滤波器 基于QUARTUS和MATLAB

+--------------------------------------+-------+
; Number of registers using SCLR       ; 0     ;
; Number of registers using SLOAD      ; 96    ;
; Number of registers using ACLR       ; 152   ;
; Number of registers using ALOAD      ; 0     ;
; Number of registers using CLK_ENABLE ; 0     ;
; Number of registers using OE         ; 0     ;
; Number of registers using PRESET     ; 0     ;
+--------------------------------------+-------+


+--------------------------------+
; Analysis & Synthesis Messages  ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
    Info: Processing started: Fri May 18 15:22:27 2007
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off fir -c fir
Info: Found 2 design units and 1 entities in source file dff89.vhd
    Info: Found design unit 1: dff89-a
    Info: Found entity 1: dff89
Info: Found 2 design units and 1 entities in source file add888.vhd
    Info: Found design unit 1: add888-a
    Info: Found entity 1: add888
Info: Found 2 design units and 1 entities in source file dff15.vhd
    Info: Found design unit 1: dff15-a
    Info: Found entity 1: dff15
Info: Found 2 design units and 1 entities in source file mult52.vhd
    Info: Found design unit 1: mult52-a
    Info: Found entity 1: mult52
Info: Found 2 design units and 1 entities in source file add121313.vhd
    Info: Found design unit 1: add121313-a
    Info: Found entity 1: add121313
Info: Found 2 design units and 1 entities in source file add121414.vhd
    Info: Found design unit 1: add121414-a
    Info: Found entity 1: add121414
Info: Found 2 design units and 1 entities in source file add121616.vhd
    Info: Found design unit 1: add121616-a
    Info: Found entity 1: add121616
Info: Found 2 design units and 1 entities in source file add141616.vhd
    Info: Found design unit 1: add141616-a
    Info: Found entity 1: add141616
Info: Found 2 design units and 1 entities in source file add889.vhd
    Info: Found design unit 1: add889-a
    Info: Found entity 1: add889
Info: Found 2 design units and 1 entities in source file dff8.vhd
    Info: Found design unit 1: dff8-a
    Info: Found entity 1: dff8
Info: Found 2 design units and 1 entities in source file mult12.vhd
    Info: Found design unit 1: mult12-a
    Info: Found entity 1: mult12
Info: Found 2 design units and 1 entities in source file mult13.vhd
    Info: Found design unit 1: mult13-a
    Info: Found entity 1: mult13
Info: Found 2 design units and 1 entities in source file mult14.vhd
    Info: Found design unit 1: mult14-a
    Info: Found entity 1: mult14
Info: Found 2 design units and 1 entities in source file mult162.vhd
    Info: Found design unit 1: mult162-a
    Info: Found entity 1: mult162
Info: Found 2 design units and 1 entities in source file mult18.vhd
    Info: Found design unit 1: mult18-a
    Info: Found entity 1: mult18
Info: Found 2 design units and 1 entities in source file mult242.vhd
    Info: Found design unit 1: mult242-a
    Info: Found entity 1: mult242
Info: Found 2 design units and 1 entities in source file mult29.vhd
    Info: Found design unit 1: mult29-a
    Info: Found entity 1: mult29
Info: Found 2 design units and 1 entities in source file sub131314.vhd
    Info: Found design unit 1: sub131314-a
    Info: Found entity 1: sub131314
Info: Found 2 design units and 1 entities in source file sub141616.vhd
    Info: Found design unit 1: sub141616-a
    Info: Found entity 1: sub141616
Info: Found 1 design units and 1 entities in source file fir.bdf
    Info: Found entity 1: fir
Warning: VHDL Process Statement warning at mult12.vhd(23): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult12.vhd(23): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult12.vhd(26): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult12.vhd(26): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult18.vhd(24): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult18.vhd(24): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult18.vhd(27): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult18.vhd(27): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult13.vhd(24): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult13.vhd(24): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult13.vhd(27): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult13.vhd(27): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult29.vhd(27): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult29.vhd(27): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult29.vhd(27): signal s3 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult29.vhd(30): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult29.vhd(30): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult29.vhd(30): signal s3 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult52.vhd(27): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult52.vhd(27): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult52.vhd(27): signal s3 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult52.vhd(30): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult52.vhd(30): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult52.vhd(30): signal s3 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult14.vhd(26): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult14.vhd(26): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult14.vhd(26): signal s3 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult14.vhd(29): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult14.vhd(29): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult14.vhd(29): signal s3 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult162.vhd(27): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult162.vhd(27): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult162.vhd(27): signal s3 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult162.vhd(30): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult162.vhd(30): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult162.vhd(30): signal s3 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult242.vhd(29): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult242.vhd(29): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult242.vhd(29): signal s3 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult242.vhd(29): signal s4 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult242.vhd(32): signal s1 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult242.vhd(32): signal s2 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult242.vhd(32): signal s3 is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at mult242.vhd(32): signal s4 is in statement, but is not in sensitivity list
Warning: Reduced register mult162:inst33|Dout[0]~reg0 with stuck data_in port to stuck value GND
Warning: Reduced register mult52:inst31|Dout[0]~reg0 with stuck data_in port to stuck value GND
Warning: Reduced register mult12:inst26|Dout[0]~reg0 with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register dff89:inst34|Dout[7]~reg0 merged to single register dff89:inst34|Dout[8]~reg0
    Info: Duplicate register dff8:inst10|Dout[7]~reg0 merged to single register dff89:inst34|Dout[8]~reg0
    Info: Duplicate register dff8:inst10|Dout[6]~reg0 merged to single register dff89:inst34|Dout[6]~reg0
    Info: Duplicate register dff8:inst10|Dout[5]~reg0 merged to single register dff89:inst34|Dout[5]~reg0
    Info: Duplicate register dff8:inst10|Dout[4]~reg0 merged to single register dff89:inst34|Dout[4]~reg0
    Info: Duplicate register dff8:inst10|Dout[3]~reg0 merged to single register dff89:inst34|Dout[3]~reg0
    Info: Duplicate register dff8:inst10|Dout[2]~reg0 merged to single register dff89:inst34|Dout[2]~reg0
    Info: Duplicate register dff8:inst10|Dout[1]~reg0 merged to single register dff89:inst34|Dout[1]~reg0
    Info: Duplicate register dff8:inst10|Dout[0]~reg0 merged to single register dff89:inst34|Dout[0]~reg0
Info: Implemented 775 device resources after synthesis - the final resource count might be different
    Info: Implemented 10 input pins
    Info: Implemented 8 output pins
    Info: Implemented 757 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 47 warnings
    Info: Processing ended: Fri May 18 15:22:33 2007
    Info: Elapsed time: 00:00:06