📄 fir.fit.rpt
字号:
; 8 ; 7 ;
; 9 ; 4 ;
; 10 ; 38 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 7.33) ; Number of LABs (Total = 98) ;
+-------------------------------------------------+------------------------------+
; 0 ; 1 ;
; 1 ; 1 ;
; 2 ; 1 ;
; 3 ; 3 ;
; 4 ; 1 ;
; 5 ; 11 ;
; 6 ; 26 ;
; 7 ; 9 ;
; 8 ; 8 ;
; 9 ; 6 ;
; 10 ; 31 ;
+-------------------------------------------------+------------------------------+
+-----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 12.29) ; Number of LABs (Total = 98) ;
+----------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 1 ;
; 4 ; 1 ;
; 5 ; 2 ;
; 6 ; 3 ;
; 7 ; 1 ;
; 8 ; 9 ;
; 9 ; 22 ;
; 10 ; 9 ;
; 11 ; 2 ;
; 12 ; 3 ;
; 13 ; 5 ;
; 14 ; 2 ;
; 15 ; 5 ;
; 16 ; 10 ;
; 17 ; 6 ;
; 18 ; 13 ;
; 19 ; 0 ;
; 20 ; 4 ;
+----------------------------------------------+------------------------------+
+------------------+
; Fitter Messages ;
+------------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Fri May 18 15:22:35 2007
Info: Command: quartus_fit --import_settings_files=off --export_settings_files=off fir -c fir
Info: Selected device EP1C3T100C6 for design fir
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: No exact pin location assignment(s) for 18 pins of 18 total pins
Info: Pin Dout[7] not assigned to an exact location on the device
Info: Pin Dout[6] not assigned to an exact location on the device
Info: Pin Dout[5] not assigned to an exact location on the device
Info: Pin Dout[4] not assigned to an exact location on the device
Info: Pin Dout[3] not assigned to an exact location on the device
Info: Pin Dout[2] not assigned to an exact location on the device
Info: Pin Dout[1] not assigned to an exact location on the device
Info: Pin Dout[0] not assigned to an exact location on the device
Info: Pin clk not assigned to an exact location on the device
Info: Pin clear not assigned to an exact location on the device
Info: Pin Din[7] not assigned to an exact location on the device
Info: Pin Din[6] not assigned to an exact location on the device
Info: Pin Din[5] not assigned to an exact location on the device
Info: Pin Din[4] not assigned to an exact location on the device
Info: Pin Din[3] not assigned to an exact location on the device
Info: Pin Din[2] not assigned to an exact location on the device
Info: Pin Din[1] not assigned to an exact location on the device
Info: Pin Din[0] not assigned to an exact location on the device
Info: Timing requirements not specified -- optimizing all clocks equally to maximize operation frequency
Info: Performing register packing on non-logic cell registers with location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal clk to use Global clock in Pin 10
Info: Automatically promoted signal clear to use Global clock in Pin 66
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Started Fast Input/Output/OE register processing
Info: Finished Fast Input/Output/OE register processing
Info: Start DSP Scan-chain Inferencing
Info: Completed DSP scan-chain inferencing
Info: Moving registers into I/Os, LUTs, DSP and RAM blocks to improve timing and density
Info: Finished moving registers into I/Os, LUTs, DSP and RAM blocks
Info: Finished register packing
Info: Statistics of I/O pins that use the same VCCIO and VREF
Info: Number of I/O pins in group: 16 (unused VREF, 3.30 VCCIO, 8 input, 8 output, 0 bidirectional)
Info: I/O standards used: LVTTL.
Info: Details of I/O bank before I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has unused VCCIO pins. 3 total pin(s) used -- 11 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 17 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 1 total pin(s) used -- 16 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 17 pins available
Info: Details of I/O bank after I/O pin placement
Info: Statistics of I/O banks
Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 11 total pin(s) used -- 3 pins available
Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 17 pins available
Info: I/O bank number 3 does not use VREF pins and has unused VCCIO pins. 9 total pin(s) used -- 8 pins available
Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used -- 17 pins available
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time = 1 seconds
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to register delay of 8.055 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X9_Y11; Fanout = 26; REG Node = 'dff89:inst34|Dout[1]~reg0'
Info: 2: + IC(0.643 ns) + CELL(0.333 ns) = 0.976 ns; Loc. = LAB_X10_Y11; Fanout = 2; COMB Node = 'mult242:inst40|i~68COUT1'
Info: 3: + IC(0.000 ns) + CELL(0.062 ns) = 1.038 ns; Loc. = LAB_X10_Y11; Fanout = 2; COMB Node = 'mult242:inst40|i~69COUT1'
Info: 4: + IC(0.000 ns) + CELL(0.062 ns) = 1.100 ns; Loc. = LAB_X10_Y11; Fanout = 2; COMB Node = 'mult242:inst40|i~70COUT1'
Info: 5: + IC(0.000 ns) + CELL(0.062 ns) = 1.162 ns; Loc. = LAB_X10_Y11; Fanout = 2; COMB Node = 'mult242:inst40|i~71COUT1'
Info: 6: + IC(0.000 ns) + CELL(0.199 ns) = 1.361 ns; Loc. = LAB_X10_Y11; Fanout = 5; COMB Node = 'mult242:inst40|i~72COUT'
Info: 7: + IC(0.000 ns) + CELL(0.523 ns) = 1.884 ns; Loc. = LAB_X10_Y11; Fanout = 3; COMB Node = 'mult242:inst40|i~73'
Info: 8: + IC(0.912 ns) + CELL(0.443 ns) = 3.239 ns; Loc. = LAB_X11_Y10; Fanout = 2; COMB Node = 'mult242:inst40|i~85COUT1'
Info: 9: + IC(0.000 ns) + CELL(0.468 ns) = 3.707 ns; Loc. = LAB_X11_Y10; Fanout = 3; COMB Node = 'mult242:inst40|i~86'
Info: 10: + IC(0.529 ns) + CELL(0.443 ns) = 4.679 ns; Loc. = LAB_X12_Y10; Fanout = 2; COMB Node = 'mult242:inst40|i~99COUT1'
Info: 11: + IC(0.000 ns) + CELL(0.468 ns) = 5.147 ns; Loc. = LAB_X12_Y10; Fanout = 2; COMB Node = 'mult242:inst40|i~100'
Info: 12: + IC(0.952 ns) + CELL(0.645 ns) = 6.744 ns; Loc. = LAB_X11_Y12; Fanout = 2; COMB Node = 'mult242:inst40|i~28COUT'
Info: 13: + IC(0.000 ns) + CELL(0.523 ns) = 7.267 ns; Loc. = LAB_X11_Y12; Fanout = 1; COMB Node = 'mult242:inst40|i~29'
Info: 14: + IC(0.699 ns) + CELL(0.089 ns) = 8.055 ns; Loc. = LAB_X10_Y12; Fanout = 1; REG Node = 'mult242:inst40|Dout[14]~reg0'
Info: Total cell delay = 4.320 ns ( 53.63 % )
Info: Total interconnect delay = 3.735 ns ( 46.37 % )
Info: Estimated interconnect usage is 9% of the available device resources
Info: Fitter placement operations ending: elapsed time = 8 seconds
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time = 0 seconds
Info: Completed Fixed Delay Chain Operation
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Fri May 18 15:22:52 2007
Info: Elapsed time: 00:00:17
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